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Searched refs:amdgpu_ring_write (Results 1 – 25 of 31) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Djpeg_v1_0.c182 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_start()
184 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
186 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
187 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
201 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_end()
203 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
205 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
206 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
224 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_emit_fence()
226 amdgpu_ring_write(ring, seq); in jpeg_v1_0_decode_ring_emit_fence()
[all …]
Djpeg_v2_0.c461 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
463 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
465 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
467 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
479 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
481 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
483 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
485 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
501 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
503 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
[all …]
Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
493 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
494 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
497 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
498 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
502 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
505 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
506 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
[all …]
Duvd_v4_2.c177 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
178 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
181 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
182 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
185 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
186 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
193 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
[all …]
Duvd_v3_1.c92 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib()
93 amdgpu_ring_write(ring, ib->gpu_addr); in uvd_v3_1_ring_emit_ib()
94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib()
95 amdgpu_ring_write(ring, ib->length_dw); in uvd_v3_1_ring_emit_ib()
111 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
112 amdgpu_ring_write(ring, seq); in uvd_v3_1_ring_emit_fence()
113 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
114 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v3_1_ring_emit_fence()
115 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
116 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v3_1_ring_emit_fence()
[all …]
Duvd_v5_0.c174 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
175 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
178 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
190 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
[all …]
Dsdma_v2_4.c236 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
239 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
260 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
264 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
265 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
266 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
267 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
287 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
290 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
[all …]
Dsi_dma.c73 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
74 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
75 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
76 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
96 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
97 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
98 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
99 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
103 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
104 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
[all …]
Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
558 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
559 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
563 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
564 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
568 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
569 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
572 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
574 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
576 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
[all …]
Dcik_sdma.c208 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
211 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
233 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
236 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
258 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
[all …]
Dvcn_v1_0.c1420 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1422 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1423 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1425 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1439 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1441 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1459 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1461 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1462 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1464 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
[all …]
Dvcn_v2_0.c1375 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1376 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1377 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1378 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1392 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1393 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1411 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1412 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1430 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1431 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
[all …]
Dsdma_v5_0.c268 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
269 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
270 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
271 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
273 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_0_ring_init_cond_exec()
385 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
388 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
410 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); in sdma_v5_0_ring_emit_ib()
411 amdgpu_ring_write(ring, 0); in sdma_v5_0_ring_emit_ib()
412 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV | in sdma_v5_0_ring_emit_ib()
[all …]
Dsdma_v5_2.c221 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
222 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
223 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
224 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
226 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_2_ring_init_cond_exec()
338 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
341 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
370 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_2_ring_emit_ib()
373 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
374 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
[all …]
Dsdma_v3_0.c410 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
413 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
434 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
440 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
441 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
[all …]
Dgfx_v7_0.c2102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2103 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2104 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2149 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2150 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2153 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2154 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2155 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2156 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2157 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
[all …]
Dgfx_v8_0.c853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
854 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
855 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4193 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4194 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4196 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4197 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4198 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4203 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4206 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
[all …]
Dgfx_v6_0.c1807 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1808 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ring()
1809 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1830 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1840 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1841 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1842 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1843 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1844 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
[all …]
Dgfx_v9_0.c810 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
811 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
815 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
817 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
819 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v9_0_kiq_set_resources()
820 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v9_0_kiq_set_resources()
821 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
822 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
833 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
835 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_0_kiq_map_queues()
[all …]
Dvce_v3_0.c842 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v3_0_ring_emit_ib()
843 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
844 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
845 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
846 amdgpu_ring_write(ring, ib->length_dw); in vce_v3_0_ring_emit_ib()
852 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); in vce_v3_0_emit_vm_flush()
853 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
854 amdgpu_ring_write(ring, pd_addr >> 12); in vce_v3_0_emit_vm_flush()
856 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); in vce_v3_0_emit_vm_flush()
857 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
[all …]
Dvce_v4_0.c953 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
954 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
955 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
956 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
957 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
965 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
966 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
967 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
968 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
969 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
[all …]
Dsdma_v4_0.c830 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
833 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
854 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
857 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
858 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
859 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
860 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
861 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
871 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
877 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
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Dgfx_v10_0.c3219 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
3220 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
3222 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3223 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
3224 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx10_kiq_set_resources()
3225 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx10_kiq_set_resources()
3226 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
3227 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
3238 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
3240 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx10_kiq_map_queues()
[all …]
Damdgpu_vce.c1051 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1052 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1053 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1054 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1069 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1070 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1071 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1072 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1073 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1074 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
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Damdgpu_amdkfd_gfx_v10.c332 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
333 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
343 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
345 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_hiq_mqd_load()
346 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
347 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_hiq_mqd_load()
348 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()

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