Searched refs:STMP_OFFSET_REG_CLR (Results 1 – 10 of 10) sorted by relevance
101 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_map_ts_channel()125 ts->base + LRADC_CH(ch) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()141 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()183 ts->base + LRADC_CH(ch1) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()185 ts->base + LRADC_CH(ch2) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()195 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()283 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_touch_detection()305 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_x_pos()331 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_y_pos()357 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_pressure()[all …]
90 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()92 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()175 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_interrupt()198 STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()200 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()241 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_remove()348 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()352 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()391 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_resume()
156 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()157 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()165 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()169 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()192 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()405 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_handle_irq()440 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; in mxs_lradc_adc_configure_trigger()496 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()498 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()510 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()[all …]
30 writel(mask, addr + STMP_OFFSET_REG_CLR); in stmp_clear_poll_bit()49 writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR); in stmp_reset_block()
12 #define STMP_OFFSET_REG_CLR 0x8 macro
69 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()99 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
71 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_disable()83 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_acknowledge()
305 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()371 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()399 STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()
308 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()311 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()357 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()372 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()
188 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); in mxs_mmc_irq_handler()527 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()529 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()
