Lines Matching refs:STMP_OFFSET_REG_CLR

156 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
157 	writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
165 		       adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
169 	       adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
192 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
405 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_handle_irq()
440 	const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;  in mxs_lradc_adc_configure_trigger()
496 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
498 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
510 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
511 	writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
526 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
529 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
532 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()