Searched refs:Pixel (Results 1 – 25 of 32) sorted by relevance
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1 Freescale Pixel Pipeline4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
50 0x6001c800 0x100 /* Pixel prediction block */
90 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
25 c) sclk_pixel: Pixel special clock, one of the two possible inputs of48 j) pixel_clko: Pixel clock generated by HDMI-PHY.
14 - pixel-clock-frequency: Pixel clock frequency.
4 Square Pixel for Color Cameras. It is programmable through I2C and 4-wire
55 - pclk-sample: Pixel clock polarity. Defaults to output on the falling edge.
15 Pixel Valve (DRM CRTC)
39 Pixel rate in the source pads of the subdev. This control is
133 - IN: Pixel format for which the frame intervals are enumerated.
149 - IN: Pixel format for which the frame sizes are enumerated.
109 - Graphics content. Pixel data should be passed unfiltered and
396 Pixel format erratum.
114 - Pixel clock in Hz. Ex. 74.25MHz->74250000
55 The Pixel lightbar has a number of built-in sequences
151 tristate "Chromebook Pixel's lightbar support"155 This option exposes the Chromebook Pixel's lightbar to
34 imx-pxp i.MX Pixel Pipeline (PXP)
39 hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
20 /* Pixel clock, porches, etc */
33 Pixel clock in picoseconds
124 Pixel values are encoded as indices into a colormap that stores red, green and268 Pixel values are bits_per_pixel wide and are split in non-overlapping red,
1713 #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ argument1714 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
6 and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
201 tristate "i.MX Pixel Pipeline (PXP)"206 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
