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Searched refs:PIPE_B (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/i915/gvt/
Dhandlers.c2021 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
2026 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2031 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
2036 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2041 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2046 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2050 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
2054 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
2058 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); in init_generic_mmio_info()
2081 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
Dreg.h74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
83 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
Ddisplay.c49 pipe = PIPE_B; in get_edp_pipe()
441 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
Dcmd_parser.c1253 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1255 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1311 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1325 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
Dinterrupt.c454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
/Linux-v5.10/drivers/gpu/drm/i915/
Di915_pci.c105 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_B] = CURSOR_B_OFFSET, \
118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
398 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
449 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all …]
Dintel_pm.c501 case PIPE_B: in vlv_get_fifo_size()
980 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
987 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1042 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1055 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1056 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
Di915_reg.h8323 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8326 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8329 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8332 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8351 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8354 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8357 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8360 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8376 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8379 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
Dintel_device_info.c400 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
426 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
471 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
Di915_trace.h45 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
72 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
169 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
Di915_irq.c555 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1335 case PIPE_B: in i9xx_pipestat_irq_ack()
1763 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
3569 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3745 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3863 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c805 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
817 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
838 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
847 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
860 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
970 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
Dintel_pipe_crc.c182 case PIPE_B: in vlv_pipe_crc_ctl_reg()
246 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dintel_display_power.c1250 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1251 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1257 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1265 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1566 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1696 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
3092 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3293 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3375 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3435 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dintel_display.h87 PIPE_B, enumerator
106 TRANSCODER_B = PIPE_B,
Dvlv_dsi.c1025 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1050 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1863 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
Dintel_lvds.c909 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
Dintel_sprite.c1114 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
3201 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
3250 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dintel_dp.c866 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
1000 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3981 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4554 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
7684 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
7687 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
7954 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in intel_dp_init()
Dintel_display_types.h1488 case PIPE_B: in vlv_pipe_to_channel()
Dicl_dsi.c799 case PIPE_B: in gen11_dsi_configure_transcoder()
1618 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
Dintel_display.c1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B), in chv_enable_pll()
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
5785 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
5809 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
7490 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
7854 case PIPE_B: in ilk_check_fdi_lanes()
7879 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
8456 if (pipe == PIPE_B) in vlv_prepare_pll()
[all …]
Dintel_panel.c569 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1784 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
/Linux-v5.10/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1059 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1302 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()

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