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Searched refs:GRBM_GFX_INDEX (Results 1 – 25 of 27) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/amd/amdkfd/
Dcik_regs.h69 #define GRBM_GFX_INDEX 0x30800 macro
Dkfd_dbgdev.c653 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq()
677 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq()
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4.c99 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh()
102 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh()
106 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
112 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
Damdgpu_amdkfd_gfx_v8.c590 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
592 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
594 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Dvce_v4_0.c712 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
717 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
722 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
904 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
923 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
Damdgpu_amdkfd_gfx_v10.c723 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Damdgpu_amdkfd_gfx_v9.c671 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
673 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
Damdgpu_amdkfd_gfx_v10_3.c633 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
635 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
637 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
Dvce_v3_0.c824 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
Dgfx_v8_0.c3436 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3438 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3441 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3443 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
3446 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3448 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
Dgfx_v9_0.c2416 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2418 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh()
2421 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2423 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
2426 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2428 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
Dsid.h996 #define GRBM_GFX_INDEX 0x200B macro
Dgfx_v10_0.c4549 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v10_0_select_se_sh()
4552 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v10_0_select_se_sh()
4556 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
4559 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
4562 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
4565 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
Dgfx_v6_0.c1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v6_0_select_se_sh()
1309 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v6_0_select_se_sh()
Dgfx_v7_0.c1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v7_0_select_se_sh()
1596 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v7_0_select_se_sh()
/Linux-v5.10/drivers/gpu/drm/radeon/
Dcypress_dpm.c127 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
154 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
188 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
209 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
Dni.c1095 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1115 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1124 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
Dnid.h295 #define GRBM_GFX_INDEX 0x802C macro
Dsid.h998 #define GRBM_GFX_INDEX 0x802C macro
Dcikd.h1627 #define GRBM_GFX_INDEX 0x30800 macro
Devergreen.c3465 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3486 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3495 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
Devergreend.h412 #define GRBM_GFX_INDEX 0x802C macro
Dsi.c2964 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh()
4423 case GRBM_GFX_INDEX: in si_vm_reg_valid()
/Linux-v5.10/drivers/gpu/drm/radeon/reg_srcs/
Devergreen2 0x0000802C GRBM_GFX_INDEX
Dcayman2 0x0000802C GRBM_GFX_INDEX

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