Searched refs:DSPCNTR (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.10/drivers/gpu/drm/i915/gvt/ |
| D | fb_decoder.c | 213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
|
| D | display.c | 343 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
|
| D | handlers.c | 769 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
2070 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2081 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2092 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info()
|
| D | cmd_parser.c | 1279 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1345 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
|
| /Linux-v5.10/drivers/gpu/drm/i915/display/ |
| D | intel_display.c | 4484 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_update_plane()
4517 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_disable_plane()
4546 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
9332 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
9451 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
18142 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & in i830_disable_pipe()
18145 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & in i830_disable_pipe()
18148 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & in i830_disable_pipe()
19039 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)); in intel_display_capture_error_state()
|
| /Linux-v5.10/drivers/gpu/drm/i915/ |
| D | intel_pm.c | 6874 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
6875 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
|
| D | i915_reg.h | 6518 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro
|
