Searched refs:DDI_BUF_CTL_ENABLE (Results 1 – 6 of 6) sorted by relevance
262 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()314 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
547 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { in ddi_buf_ctl_mmio_write()574 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && in fdi_auto_training_started()
1435 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); in hsw_fdi_link_train()1481 temp &= ~DDI_BUF_CTL_ENABLE; in hsw_fdi_link_train()1516 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); in intel_ddi_init_dp_buf_reg()1959 if (!(tmp & DDI_BUF_CTL_ENABLE)) in intel_ddi_get_encoder_pipes()3608 if (val & DDI_BUF_CTL_ENABLE) { in intel_disable_ddi_buf()3609 val &= ~DDI_BUF_CTL_ENABLE; in intel_disable_ddi_buf()3941 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); in intel_enable_ddi_hdmi()4124 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { in intel_ddi_prepare_link_retrain()4126 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); in intel_ddi_prepare_link_retrain()4150 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
512 tmp |= DDI_BUF_CTL_ENABLE; in gen11_dsi_enable_ddi_buffer()1308 tmp &= ~DDI_BUF_CTL_ENABLE; in gen11_dsi_disable_port()
72 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; in assert_hdmi_port_disabled()
9994 #define DDI_BUF_CTL_ENABLE (1 << 31) macro
