Searched refs:CLK_SCLK_UART0 (Results 1 – 25 of 27) sorted by relevance
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| /Linux-v5.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 22 #define CLK_SCLK_UART0 128 macro
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| D | exynos5250.h | 42 #define CLK_SCLK_UART0 146 macro
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| D | exynos7-clk.h | 37 #define CLK_SCLK_UART0 3 macro
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| D | exynos4.h | 64 #define CLK_SCLK_UART0 151 macro
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| D | exynos5420.h | 29 #define CLK_SCLK_UART0 128 macro
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| D | exynos3250.h | 255 #define CLK_SCLK_UART0 247 macro
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| D | exynos5433.h | 437 #define CLK_SCLK_UART0 36 macro
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5410-clock.txt | 48 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos3250-clock.txt | 55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| D | exynos5433-clock.txt | 503 <&cmu_peric CLK_SCLK_UART0>;
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| /Linux-v5.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 212 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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| D | clk-exynos5250.c | 491 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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| D | clk-exynos3250.c | 567 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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| D | clk-exynos7.c | 365 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
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| D | clk-exynos4.c | 777 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
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| D | clk-exynos5420.c | 979 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | exynos3250-artik5.dtsi | 404 assigned-clocks = <&cmu CLK_SCLK_UART0>;
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| D | exynos5410.dtsi | 344 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos3250-monk.dts | 457 assigned-clocks = <&cmu CLK_SCLK_UART0>;
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| D | exynos3250-rinato.dts | 666 assigned-clocks = <&cmu CLK_SCLK_UART0>;
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| D | exynos3250.dtsi | 504 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| D | exynos4.dtsi | 453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos5250.dtsi | 1195 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos5420.dtsi | 1329 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| /Linux-v5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos7.dtsi | 175 <&clock_top0 CLK_SCLK_UART0>;
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