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Searched refs:BIT_1 (Results 1 – 25 of 35) sorted by relevance

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/Linux-v5.10/drivers/scsi/
Dqla1280.h18 #define BIT_1 0x2 macro
121 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
135 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
142 #define PCI_INT BIT_1 /* PCI interrupt */
147 #define NV_SELECT BIT_1
159 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
176 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
568 #define RF_FULL BIT_1 /* Full */
966 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
Dqla1280.c1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1690 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1704 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1708 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1842 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1909 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1923 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2143 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2216 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
[all …]
/Linux-v5.10/drivers/scsi/qla2xxx/
Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
456 #define BD_READ_DATA BIT_1
494 #define CF_READ_DATA BIT_1
536 #define TMF_READ_DATA BIT_1
965 #define TCF_TARGET_RESET BIT_1
1167 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1237 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1245 #define GPEX_ENABLE (BIT_1|BIT_0)
1368 #define MDBS_ID_ACQUIRED BIT_1
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Dqla_def.h82 #define BIT_1 0x2 macro
204 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
224 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
481 #define SRB_LOGIN_COND_PLOGI BIT_1
526 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
714 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
732 #define NVR_SELECT BIT_1
989 #define MBX_DMA_OUT BIT_1
1002 #define MBX_DMA_OUT BIT_1
1124 #define FO1_AE_ALL_LIP_RESET BIT_1
[all …]
Dqla_target.h225 #define ATIO_EXEC_READ BIT_1
469 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
830 TRC_DO_WORK = BIT_1,
956 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
Dqla_nvme.h60 #define CF_READ_DATA BIT_1
Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
Dqla_init.c3890 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3894 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3904 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
3905 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
3910 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
3912 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
3922 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
3923 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4216 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
4637 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
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Dqla_mbx.c750 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
757 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1840 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2340 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2473 if (opt & BIT_1) in qla24xx_login_fabric()
2533 mb[1] |= BIT_1; in qla24xx_login_fabric()
2542 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
4261 rval = BIT_1; in qla2x00_send_change_request()
4264 rval = BIT_1; in qla2x00_send_change_request()
5662 mcp->mb[2] = BIT_1; in qla24xx_set_fcp_prio()
[all …]
Dqla_mid.c877 options |= BIT_1; in qla25xx_create_rsp_que()
Dqla_attr.c1389 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()
1411 options |= BIT_1; in qla2x00_beacon_config_store()
Dqla_isr.c1806 else if (le16_to_cpu(mbx->mb1) & BIT_1) in qla2x00_mbx_iocb_entry()
2933 if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) { in qla2x00_status_entry()
/Linux-v5.10/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1
Dqlcnic_ctx.c1346 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1358 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1359 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
Dqlcnic_83xx_hw.h531 #define QLC_REGISTER_DCB_AEN BIT_1
Dqlcnic.h913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
1315 #define QLCNIC_SWITCH_ENABLE BIT_1
Dqlcnic_hw.c819 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
1037 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
Dqlcnic_minidump.c24 #define QLCNIC_DUMP_RWCRB BIT_1
753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
Dqlcnic_sriov_pf.c390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()
701 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
Dqlcnic_83xx_hw.c2017 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3531 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()
3562 #define QLCNIC_83XX_ADD_PORT1 BIT_1
Dqlcnic_83xx_init.c1022 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1
/Linux-v5.10/drivers/scsi/qla4xxx/
Dql4_def.h82 #define BIT_1 0x2 macro
Dql4_os.c3540 sess->erl |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3553 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3671 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3680 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3681 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3777 sess->erl |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
3790 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
8907 if (PCI_FUNC(ha->pdev->devfn) & BIT_1) in qla4xxx_prevent_other_port_reinit()
Dql4_fw.h61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */

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