Searched refs:we_mask (Results 1 – 7 of 7) sorted by relevance
828 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES); in dpaa_eth_cgr_init()842 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); in dpaa_eth_cgr_init()998 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL); in dpaa_fq_init()1009 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ); in dpaa_fq_init()1022 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); in dpaa_fq_init()1034 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); in dpaa_fq_init()1043 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH); in dpaa_fq_init()1053 initfq.we_mask |= in dpaa_fq_init()1072 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); in dpaa_fq_init()1078 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); in dpaa_fq_init()[all …]
1776 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) { in qman_init_fq()1778 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH) in qman_init_fq()1802 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB); in qman_init_fq()1808 if (!(be16_to_cpu(mcc->initfq.we_mask) & in qman_init_fq()1810 mcc->initfq.we_mask |= in qman_init_fq()1831 if (!(be16_to_cpu(mcc->initfq.we_mask) & in qman_init_fq()1833 mcc->initfq.we_mask |= in qman_init_fq()1853 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) { in qman_init_fq()1859 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID) in qman_init_fq()2359 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG); in qman_create_cgr()[all …]
409 opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | in init_handler()
190 opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | in create_caam_req_fq()632 opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ | in alloc_rsp_fq_cpu()671 opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | in init_cgr()
968 u8 we_mask, u8 cdan_en, in qbman_swp_CDAN_set() argument981 p->we = we_mask; in qbman_swp_CDAN_set()
184 u8 we_mask, u8 cdan_en,
604 __be16 we_mask; /* Write Enable Mask */ member613 __be16 we_mask; /* Write Enable Mask */ member
