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Searched refs:timer_of_base (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/clocksource/
Dtimer-npcm7xx.c61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
88 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
90 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
103 writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); in npcm7xx_timer_periodic()
106 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
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Dsun4i_timer.c89 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_shutdown()
98 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_oneshot()
99 sun4i_clkevt_time_start(timer_of_base(to), 0, false); in sun4i_clkevt_set_oneshot()
108 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_set_periodic()
109 sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to)); in sun4i_clkevt_set_periodic()
110 sun4i_clkevt_time_start(timer_of_base(to), 0, true); in sun4i_clkevt_set_periodic()
120 sun4i_clkevt_time_stop(timer_of_base(to), 0); in sun4i_clkevt_next_event()
121 sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS); in sun4i_clkevt_next_event()
122 sun4i_clkevt_time_start(timer_of_base(to), 0, false); in sun4i_clkevt_next_event()
137 sun4i_timer_clear_interrupt(timer_of_base(to)); in sun4i_timer_interrupt()
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Dtimer-sprd.c84 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_next_event()
85 sprd_timer_update_counter(timer_of_base(to), cycles); in sprd_timer_set_next_event()
86 sprd_timer_enable(timer_of_base(to), 0); in sprd_timer_set_next_event()
95 sprd_timer_disable(timer_of_base(to)); in sprd_timer_set_periodic()
96 sprd_timer_update_counter(timer_of_base(to), timer_of_period(to)); in sprd_timer_set_periodic()
97 sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE); in sprd_timer_set_periodic()
106 sprd_timer_disable(timer_of_base(to)); in sprd_timer_shutdown()
115 sprd_timer_clear_interrupt(timer_of_base(to)); in sprd_timer_interrupt()
118 sprd_timer_disable(timer_of_base(to)); in sprd_timer_interrupt()
152 sprd_timer_enable_interrupt(timer_of_base(&to)); in sprd_timer_init()
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Dtimer-mediatek.c65 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
66 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
148 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_stop()
149 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + in mtk_gpt_clkevt_time_stop()
156 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer)); in mtk_gpt_clkevt_time_setup()
165 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); in mtk_gpt_clkevt_time_start()
167 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_start()
178 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_clkevt_time_start()
217 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); in mtk_gpt_interrupt()
227 timer_of_base(to) + GPT_CTRL_REG(timer)); in mtk_gpt_setup()
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Dtimer-atcpit100.c127 val = readl(timer_of_base(to) + CH_EN); in atcpit100_clkevt_next_event()
128 writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN); in atcpit100_clkevt_next_event()
129 writel(evt, timer_of_base(to) + CH0_REL); in atcpit100_clkevt_next_event()
130 writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); in atcpit100_clkevt_next_event()
139 atcpit100_clkevt_time_setup(timer_of_base(to), timer_of_period(to)); in atcpit100_clkevt_set_periodic()
140 atcpit100_clkevt_time_start(timer_of_base(to)); in atcpit100_clkevt_set_periodic()
148 atcpit100_clkevt_time_stop(timer_of_base(to)); in atcpit100_clkevt_shutdown()
157 writel(~0x0, timer_of_base(to) + CH0_REL); in atcpit100_clkevt_set_oneshot()
158 val = readl(timer_of_base(to) + CH_EN); in atcpit100_clkevt_set_oneshot()
159 writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); in atcpit100_clkevt_set_oneshot()
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Dtimer-stm32.c101 writel_relaxed(0, timer_of_base(to) + TIM_DIER); in stm32_clock_event_disable()
114 writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); in stm32_timer_start()
132 next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; in stm32_clock_event_set_next_event()
133 writel_relaxed(next, timer_of_base(to) + TIM_CCR1); in stm32_clock_event_set_next_event()
134 now = readl_relaxed(timer_of_base(to) + TIM_CNT); in stm32_clock_event_set_next_event()
139 writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); in stm32_clock_event_set_next_event()
167 writel_relaxed(0, timer_of_base(to) + TIM_SR); in stm32_clock_event_handler()
192 writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
194 width = readl_relaxed(timer_of_base(to) + TIM_ARR); in stm32_timer_set_width()
222 writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); in stm32_timer_set_prescaler()
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Dtimer-of.h49 static inline void __iomem *timer_of_base(struct timer_of *to) in timer_of_base() function