Searched refs:rt_sysc_r32 (Results 1 – 15 of 15) sorted by relevance
315 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()316 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()317 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()328 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()332 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()336 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()340 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()390 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()397 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()401 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
245 if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { in mt7620_pci_hw_init()
127 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) in ralink_clk_init()132 clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); in ralink_clk_init()139 fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; in ralink_clk_init()140 syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); in ralink_clk_init()
35 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_assert_device()50 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); in ralink_deassert_device()
388 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in mt7620_get_xtal_rate()400 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); in mt7620_get_periph_rate()416 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); in mt7620_get_cpu_pll_rate()442 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); in mt7620_get_pll_rate()459 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_cpu_rate()492 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in mt7620_get_sys_rate()580 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); in ralink_clk_init()
132 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()185 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); in ralink_clk_init()
45 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); in ralink_clk_init()
72 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); in ralink_clk_init()
43 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function50 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
137 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()
106 if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) { in mt7621_hw_init()129 val = rt_sysc_r32(SYSC_REG_CFG); in mt7621_hw_init()
99 if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \106 if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \245 unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); in set_phy_for_ssc()
102 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in mt7621_wdt_bootcause()
116 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in rt288x_wdt_bootcause()
176 mode = rt_sysc_r32(reg); in rt2880_pmx_group_enable()
