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Searched refs:reg_base (Results 1 – 25 of 282) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
39 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
41 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
49 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
51 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
65 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
73 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
76 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
83 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
[all …]
/Linux-v4.19/drivers/gpio/
Dgpio-bcm-kona.c68 void __iomem *reg_base; member
84 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
87 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
88 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
100 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
102 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
116 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
118 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
126 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
129 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
Dgpio-amdpt.c30 void __iomem *reg_base; member
43 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
51 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
66 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
68 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
98 pt_gpio->reg_base = devm_ioremap_resource(dev, res_mem); in pt_gpio_probe()
99 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
101 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
105 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
106 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
[all …]
Dgpio-menz127.c37 void __iomem *reg_base; member
72 db_en = readl(priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
82 writel(db_en, priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
83 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); in men_z127_debounce()
98 od_en = readl(priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
106 writel(od_en, priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
151 men_z127_gpio->reg_base = ioremap(men_z127_gpio->mem->start, in men_z127_probe()
153 if (men_z127_gpio->reg_base == NULL) { in men_z127_probe()
161 men_z127_gpio->reg_base + MEN_Z127_PSR, in men_z127_probe()
162 men_z127_gpio->reg_base + MEN_Z127_CTRL, in men_z127_probe()
[all …]
/Linux-v4.19/arch/sh/drivers/pci/
Dpci-sh7780.c103 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
108 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
116 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
122 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
135 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
180 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
/Linux-v4.19/drivers/net/ethernet/cavium/thunder/
Dthunder_xcv.c50 void __iomem *reg_base; member
73 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
78 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
80 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
87 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
90 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
95 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
97 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
98 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/Linux-v4.19/drivers/ata/
Dahci_qoriq.c64 struct ccsr_ahci *reg_base; member
164 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
171 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
172 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
173 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
174 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
175 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
176 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
179 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
187 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
[all …]
Dahci_sunxi.c94 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) in ahci_sunxi_phy_init() argument
100 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
103 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
107 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
111 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
112 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
114 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
118 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
[all …]
/Linux-v4.19/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c47 void *reg_base = in lcd_spi_write() local
51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/Linux-v4.19/drivers/ide/
Dopti621.c29 static int reg_base; variable
40 inw(reg_base + 1); in write_reg()
41 inw(reg_base + 1); in write_reg()
42 outb(3, reg_base + 2); in write_reg()
43 outb(value, reg_base + reg); in write_reg()
44 outb(0x83, reg_base + 2); in write_reg()
56 inw(reg_base + 1); in read_reg()
57 inw(reg_base + 1); in read_reg()
58 outb(3, reg_base + 2); in read_reg()
59 ret = inb(reg_base + reg); in read_reg()
[all …]
/Linux-v4.19/arch/powerpc/boot/
Duartlite.c29 static void * reg_base; variable
34 out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX); in uartlite_open()
42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
43 out_be32(reg_base + ULITE_TX, c); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
65 n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base)); in uartlite_console_init()
66 if (n != sizeof(reg_base)) { in uartlite_console_init()
70 reg_base = (void *)reg_phys; in uartlite_console_init()
Dns16550.c30 static unsigned char *reg_base; variable
35 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
41 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
42 out_8(reg_base, c); in ns16550_putc()
47 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
48 return in_8(reg_base); in ns16550_getc()
53 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
61 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) in ns16550_console_init()
66 reg_base += reg_offset; in ns16550_console_init()
Dvirtex.c30 unsigned char *reg_base; in virtex_ns16550_console_init() local
35 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) in virtex_ns16550_console_init()
40 reg_base += reg_offset; in virtex_ns16550_console_init()
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
/Linux-v4.19/drivers/remoteproc/
Dqcom_q6v5_wcss.c76 void __iomem *reg_base; member
103 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
105 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
108 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
110 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
113 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
122 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
124 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
129 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
132 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
[all …]
/Linux-v4.19/drivers/clk/samsung/
Dclk-s5pv210-audss.c27 static void __iomem *reg_base; variable
46 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
56 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
77 reg_base = devm_ioremap_resource(&pdev->dev, res); in s5pv210_audss_clk_probe()
78 if (IS_ERR(reg_base)) { in s5pv210_audss_clk_probe()
80 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
123 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
134 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
138 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
141 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
Dclk-exynos-audss.c26 static void __iomem *reg_base; variable
51 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
61 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
145 reg_base = devm_ioremap_resource(dev, res); in exynos_audss_clk_probe()
146 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
147 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
193 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
204 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
208 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
212 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/Linux-v4.19/drivers/rtc/
Drtc-zynqmp.c56 void __iomem *reg_base; member
82 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); in xlnx_rtc_set_time()
84 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
94 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
105 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
112 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); in xlnx_rtc_read_time()
121 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
132 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
133 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
143 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN); in xlnx_rtc_alarm_irq_enable()
[all …]
/Linux-v4.19/arch/arm/mach-rockchip/
Drockchip.c37 void __iomem *reg_base; in rockchip_timer_init() local
44 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
45 if (reg_base) { in rockchip_timer_init()
46 writel(0, reg_base + 0x30); in rockchip_timer_init()
47 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
48 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
49 writel(1, reg_base + 0x30); in rockchip_timer_init()
51 iounmap(reg_base); in rockchip_timer_init()
/Linux-v4.19/drivers/clk/zte/
Dclk.c50 hw_cfg0 = readl_relaxed(zx_pll->reg_base); in hw_to_idx()
51 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); in hw_to_idx()
103 writel_relaxed(config->cfg0, zx_pll->reg_base); in zx_pll_set_rate()
104 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); in zx_pll_set_rate()
118 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_enable()
119 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_enable()
121 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, in zx_pll_enable()
133 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_disable()
134 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_disable()
142 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_is_enabled()
[all …]
/Linux-v4.19/drivers/input/serio/
Dsun4i-ps2.c84 void __iomem *reg_base; member
106 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
107 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
117 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
129 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
153 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
160 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/Linux-v4.19/drivers/irqchip/
Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/Linux-v4.19/drivers/spi/
Dspi-fsl-spi.c90 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
91 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
291 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
296 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
300 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
309 struct fsl_spi_reg *reg_base; in fsl_spi_bufs() local
314 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
347 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
424 struct fsl_spi_reg *reg_base; in fsl_spi_setup() local
440 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
/Linux-v4.19/drivers/fpga/
Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
187 priv->reg_base = reg_base; in alt_pr_register()
[all …]
/Linux-v4.19/arch/sparc/kernel/
Dsbus.c212 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
222 imap += reg_base; in sbus_build_irq()
237 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
240 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
243 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
247 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
274 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
279 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
280 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
348 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
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/Linux-v4.19/drivers/mtd/spi-nor/
Dcadence-quadspi.c342 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local
346 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
349 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
352 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
370 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read() local
385 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); in cqspi_command_read()
396 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); in cqspi_command_read()
404 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); in cqspi_command_read()
418 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write() local
437 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); in cqspi_command_write()
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