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Searched refs:read_csr (Results 1 – 17 of 17) sorted by relevance

/Linux-v4.19/drivers/infiniband/hw/hfi1/
Dfirmware.c287 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in __read_8051_data()
299 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); in __read_8051_data()
372 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in write_8051()
836 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
871 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
919 reg = read_csr(dd, MISC_ERR_STATUS); in run_rsa()
949 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); in get_firmware_state()
1105 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_read()
1226 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_request_slow()
1230 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); in sbus_request_slow()
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Dintr.c182 read_csr(dd, DC_DC8051_STS_REMOTE_GUID); in handle_linkup_change()
184 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & in handle_linkup_change()
187 read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & in handle_linkup_change()
190 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) & in handle_linkup_change()
Dchip.h602 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
614 return read_csr(dd, offset0 + (0x100 * ctxt)); in read_kctxt_csr()
649 return read_csr(dd, offset0 + (0x1000 * ctxt)); in read_uctxt_csr()
661 return read_csr(dd, RCV_CONTEXTS); in chip_rcv_contexts()
666 return read_csr(dd, SEND_CONTEXTS); in chip_send_contexts()
671 return read_csr(dd, SEND_DMA_ENGINES); in chip_sdma_engines()
676 return read_csr(dd, SEND_PIO_MEM_SIZE); in chip_pio_mem_size()
681 return read_csr(dd, SEND_DMA_MEM_SIZE); in chip_sdma_mem_size()
686 return read_csr(dd, RCV_ARRAY_CNT); in chip_rcv_array_count()
Dqsfp.c74 reg = read_csr(dd, target_oe); in hfi1_setsda()
87 (void)read_csr(dd, target_oe); in hfi1_setsda()
98 reg = read_csr(dd, target_oe); in hfi1_setscl()
111 (void)read_csr(dd, target_oe); in hfi1_setscl()
124 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getsda()
138 reg = read_csr(bus->controlling_dd, target_in); in hfi1_getscl()
688 reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); in qsfp_mod_present()
Dpcie.c930 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
960 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
1094 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1323 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1325 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1389 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
Dchip.c1331 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) in read_csr() function
1379 ret = read_csr(dd, csr); in read_write_csr()
5672 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ in handle_send_egress_err_info()
5673 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); in handle_send_egress_err_info()
6335 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); in handle_8051_request()
6363 (void)read_csr(dd, DCC_CFG_RESET); in handle_8051_request()
6390 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vau()
6405 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vl15()
6478 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); in lcb_shutdown()
6479 reg = read_csr(dd, DCC_CFG_RESET); in lcb_shutdown()
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Dplatform.c61 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); in validate_scratch_checksum()
80 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH + (8 * i)); in validate_scratch_checksum()
90 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); in validate_scratch_checksum()
106 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH_1); in save_platform_config_fields()
136 temp_scratch = read_csr(dd, dd->hfi1_id ? ASIC_CFG_SCRATCH_3 : in save_platform_config_fields()
Dpio.c68 sendctrl = read_csr(dd, SEND_CTRL); in __cm_reset()
93 reg = read_csr(dd, SEND_CTRL); in pio_send_control()
133 (void)read_csr(dd, SEND_CTRL); /* flush write */ in pio_send_control()
1009 reg = read_csr(dd, sc->hw_context * 8 + in sc_wait_for_packet_egress()
1232 reg = read_csr(dd, SEND_PIO_INIT_CTXT); in pio_init_wait_progress()
Deprom.c94 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); in read_page()
Ddebugfs.c514 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_read()
571 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
575 (void)read_csr(dd, ASIC_CFG_SCRATCH); in asic_flags_write()
Dsdma.c315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); in sdma_wait_for_packet_egress()
2079 csr = read_csr(sde->dd, reg); \
2090 csr = read_csr(sde->dd, reg + (8 * i)); \
Dmad.c1818 *val++ = read_csr(dd, SEND_SC2VLT0); in get_sc2vlt_tables()
1819 *val++ = read_csr(dd, SEND_SC2VLT1); in get_sc2vlt_tables()
1820 *val++ = read_csr(dd, SEND_SC2VLT2); in get_sc2vlt_tables()
1821 *val++ = read_csr(dd, SEND_SC2VLT3); in get_sc2vlt_tables()
3438 reg = read_csr(dd, RCV_ERR_INFO); in pma_get_opa_errorinfo()
/Linux-v4.19/drivers/net/ethernet/amd/
Dpcnet32.c246 u16 (*read_csr) (unsigned long, int); member
386 .read_csr = pcnet32_wio_read_csr,
441 .read_csr = pcnet32_dwio_read_csr,
466 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_netif_start()
700 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_suspend()
705 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { in pcnet32_suspend()
724 int csr5 = lp->a->read_csr(ioaddr, CSR5); in pcnet32_clr_suspend()
784 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180; in pcnet32_set_link_ksettings()
1061 x = a->read_csr(ioaddr, CSR15) & 0xfffc; in pcnet32_loopback_test()
1119 x = a->read_csr(ioaddr, CSR15); in pcnet32_loopback_test()
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/Linux-v4.19/drivers/firewire/
Dcore.h91 u32 (*read_csr)(struct fw_card *card, int csr_offset); member
Dcore-transaction.c1118 *data = cpu_to_be32(card->driver->read_csr(card, reg)); in handle_registers()
Dcore-cdev.c1214 cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); in ioctl_get_cycle_timer2()
Dohci.c3523 .read_csr = ohci_read_csr,