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Searched refs:rb_bufsz (Results 1 – 25 of 30) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/radeon/
Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
Dr600_dma.c124 u32 rb_bufsz; in r600_dma_resume() local
131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
Dni_dma.c191 u32 rb_bufsz; in cayman_dma_resume() local
210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
Dcik_sdma.c369 u32 rb_bufsz; in cik_sdma_gfx_resume() local
388 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dr600.c2713 u32 rb_bufsz; in r600_cp_resume() local
2723 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2724 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2775 u32 rb_bufsz; in r600_ring_init() local
2779 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2780 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3465 u32 rb_bufsz; in r600_ih_ring_init() local
3468 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3469 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3671 int rb_bufsz; in r600_irq_init() local
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Dsi.c3648 u32 rb_bufsz; in si_cp_resume() local
3665 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3666 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3696 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3697 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3720 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3721 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
5977 int rb_bufsz; in si_irq_init() local
6008 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
6012 (rb_bufsz << 1)); in si_irq_init()
Dr100.c1107 unsigned rb_bufsz; in r100_cp_init() local
1129 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()
1130 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()
1163 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c68 u32 rb_bufsz; in amdgpu_ih_ring_init() local
72 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
73 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
Dsi_ih.c60 int rb_bufsz; in si_ih_irq_init() local
72 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
76 (rb_bufsz << 1) | in si_ih_irq_init()
Dcik_ih.c106 int rb_bufsz; in cik_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
129 (rb_bufsz << 1)); in cik_ih_irq_init()
Duvd_v4_2.c260 uint32_t rb_bufsz; in uvd_v4_2_start() local
370 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
371 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
372 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
Dcz_ih.c106 int rb_bufsz; in cz_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
Diceland_ih.c106 int rb_bufsz; in iceland_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
Dtonga_ih.c102 int rb_bufsz; in tonga_ih_irq_init() local
126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
Dvega10_ih.c90 int rb_bufsz; in vega10_ih_irq_init() local
111 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in vega10_ih_irq_init()
114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_irq_init()
Duvd_v5_0.c297 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
394 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
Dsi_dma.c132 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
143 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
144 rb_cntl = rb_bufsz << 1; in si_dma_start()
Dcik_sdma.c432 u32 rb_bufsz; in cik_sdma_gfx_resume() local
458 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
459 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dsdma_v2_4.c408 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
432 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
434 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
Dgfx_v6_0.c2084 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2100 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2101 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2184 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2192 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2193 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2212 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2213 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
Duvd_v6_0.c714 uint32_t rb_bufsz, tmp; in uvd_v6_0_start() local
823 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
824 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
Dsdma_v3_0.c644 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
671 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
Dvcn_v1_0.c620 uint32_t rb_bufsz, tmp; in vcn_v1_0_start() local
732 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start()
733 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start()
Dsdma_v4_0.c620 u32 rb_bufsz; in sdma_v4_0_gfx_resume() local
635 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v4_0_gfx_resume()
637 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_gfx_resume()
Duvd_v7_0.c930 uint32_t rb_bufsz, tmp; in uvd_v7_0_start() local
1058 rb_bufsz = order_base_2(ring->ring_size); in uvd_v7_0_start()
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()

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