2713 	u32 rb_bufsz;  in r600_cp_resume()  local
2723 	rb_bufsz = order_base_2(ring->ring_size / 8);  in r600_cp_resume()
2724 	tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;  in r600_cp_resume()
2775 	u32 rb_bufsz;  in r600_ring_init()  local
2779 	rb_bufsz = order_base_2(ring_size / 8);  in r600_ring_init()
2780 	ring_size = (1 << (rb_bufsz + 1)) * 4;  in r600_ring_init()
3465 	u32 rb_bufsz;  in r600_ih_ring_init()  local
3468 	rb_bufsz = order_base_2(ring_size / 4);  in r600_ih_ring_init()
3469 	ring_size = (1 << rb_bufsz) * 4;  in r600_ih_ring_init()
3671 	int rb_bufsz;  in r600_irq_init()  local
3705 	rb_bufsz = order_base_2(rdev->ih.ring_size / 4);  in r600_irq_init()
3709 		      (rb_bufsz << 1));  in r600_irq_init()