| /Linux-v4.19/arch/mips/ath79/ |
| D | clock.c | 248 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
317 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
323 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
325 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
333 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
335 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
337 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
343 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
345 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
[all …]
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| /Linux-v4.19/drivers/clk/mediatek/ |
| D | clk-pll.c | 68 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
88 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
92 int postdiv) in mtk_pll_set_rate_regs() argument
102 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
138 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
157 *postdiv = 1 << val; in mtk_pll_calc_values()
160 *postdiv = 1 << val; in mtk_pll_calc_values()
161 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
178 u32 postdiv; in mtk_pll_set_rate() local
180 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
[all …]
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| /Linux-v4.19/arch/mips/ar7/ |
| D | clock.c | 85 u32 postdiv; member
112 int *postdiv, int *mul) in approximate() argument
123 *postdiv = k; in approximate()
128 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
137 *postdiv = tmp_base / tmp_gcd; in calculate()
140 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
144 if (base / *prediv * *mul / *postdiv != target) { in calculate()
145 approximate(base, target, prediv, postdiv, mul); in calculate()
146 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
153 *prediv, *postdiv, *mul); in calculate()
[all …]
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| /Linux-v4.19/drivers/clk/keystone/ |
| D | pll.c | 64 u32 postdiv; member
85 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
104 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
108 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
111 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
115 rate /= postdiv; in clk_pllclk_recalc()
176 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
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| /Linux-v4.19/arch/c6x/platforms/ |
| D | pll.c | 271 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
299 postdiv = pll_read(pll, PLLPOST); in clk_pllclk_recalc()
300 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
301 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
303 postdiv = 1; in clk_pllclk_recalc()
311 if (postdiv) in clk_pllclk_recalc()
312 rate /= postdiv; in clk_pllclk_recalc()
317 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()
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| /Linux-v4.19/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_14nm.c | 688 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
689 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
691 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
692 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
701 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
708 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
709 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
714 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
715 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
721 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_set_rate() local
[all …]
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| /Linux-v4.19/Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
21 for postdiv
30 fixed-postdiv = <2>;
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| /Linux-v4.19/arch/arm/mach-davinci/ |
| D | da850.c | 485 unsigned int postdiv; member
494 .postdiv = 1,
503 .postdiv = 1,
512 .postdiv = 1,
521 .postdiv = 2,
530 .postdiv = 3,
539 .postdiv = 5,
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| /Linux-v4.19/drivers/video/fbdev/ |
| D | gxt4500.c | 237 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
247 postdiv = pdiv1 * pdiv2; in calc_pll()
248 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
256 n = intf * postdiv / period_ps; in calc_pll()
259 t = par->refclk_ps * m * postdiv / n; in calc_pll()
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| /Linux-v4.19/drivers/clk/ |
| D | clk-axm5516.c | 55 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
59 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
62 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | vegam_smumgr.c | 681 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
700 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
702 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
705 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
758 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
760 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
768 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
777 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
779 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
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| D | polaris10_smumgr.c | 810 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
824 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
825 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
828 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
880 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
881 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
888 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
895 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
896 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
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| /Linux-v4.19/drivers/media/i2c/ |
| D | ov2659.c | 912 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
918 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
925 actual /= postdiv; in ov2659_pll_calc_params()
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/ |
| D | smu74_discrete.h | 45 uint8_t postdiv; member
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| D | smu75_discrete.h | 44 uint8_t postdiv; /* divide by 2^n */ member
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | rv770_dpm.c | 343 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) in rv770_encode_yclk_post_div() argument
347 switch (postdiv) { in rv770_encode_yclk_post_div()
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