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Searched refs:pll1 (Results 1 – 25 of 49) sorted by relevance

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/Linux-v4.19/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi56 pll1: pll1@820 { label
61 clock-output-names = "pll1", "pll1-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi434 <&pll1 0>, <&pll1 1>, <&pll1 2>;
435 clock-names = "pll0", "pll0-div2", "pll1-div4",
436 "pll1", "pll1-div2", "pll1-div4";
445 <&pll1 0>, <&pll1 1>, <&pll1 2>;
446 clock-names = "pll0", "pll0-div2", "pll1-div4",
447 "pll1", "pll1-div2", "pll1-div4";
456 <&pll1 0>, <&pll1 1>, <&pll1 2>;
457 clock-names = "pll0", "pll0-div2", "pll1-div4",
458 "pll1", "pll1-div2", "pll1-div4";
467 <&pll1 0>, <&pll1 1>, <&pll1 2>;
Dqoriq-clockgen2.dtsi55 pll1: pll1@820 { label
60 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
Dt2081si-post.dtsi544 <&pll1 0>, <&pll1 1>, <&pll1 2>;
546 "pll1", "pll1-div2", "pll1-div4";
555 <&pll1 0>, <&pll1 1>, <&pll1 2>;
557 "pll1", "pll1-div2", "pll1-div4";
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4si-post.dtsi410 <&pll1 0>, <&pll1 1>, <&pll1 2>;
412 "pll1", "pll1-div2", "pll1-div4";
Dt4240si-post.dtsi983 <&pll1 0>, <&pll1 1>, <&pll1 2>,
986 "pll1", "pll1-div2", "pll1-div4",
996 <&pll1 0>, <&pll1 1>, <&pll1 2>,
999 "pll1", "pll1-div2", "pll1-div4",
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt160 pll1: pll1@820 {
165 clock-output-names = "pll1", "pll1-div2";
172 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
173 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
182 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
Dsunxi.txt10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
148 pll1: clk@1c20000 {
150 compatible = "allwinner,sun4i-a10-pll1-clk";
153 clock-output-names = "pll1";
176 clocks = <&osc32k>, <&osc24M>, <&pll1>;
Drenesas,rcar-gen2-cpg-clocks.txt24 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
45 clock-output-names = "main", "pll0, "pll1", "pll3",
/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/Linux-v4.19/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
300 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
316 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
325 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
/Linux-v4.19/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
/Linux-v4.19/drivers/gpu/drm/tegra/
Dhdmi.c37 u32 pll1; member
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
205 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
223 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
237 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
268 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
286 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
305 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
324 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
/Linux-v4.19/drivers/clk/sirf/
Dclk-prima2.c61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
136 for (i = pll1; i < maxclk; i++) { in prima2_clk_init()
Dclk-atlas6.c62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
137 for (i = pll1; i < maxclk; i++) { in atlas6_clk_init()
/Linux-v4.19/sound/soc/codecs/
Dtscs454.c132 struct pll pll1; member
293 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
445 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
469 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
694 mutex_lock(&tscs454->pll1.lock); in pll_connected()
695 users = tscs454->pll1.users; in pll_connected()
696 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
721 bool pll1; in pll_power_event() local
727 pll1 = true; in pll_power_event()
729 pll1 = false; in pll_power_event()
[all …]
/Linux-v4.19/arch/arm/mach-davinci/
Ddm646x.c643 void __iomem *pll1, *psc; in dm646x_init_time() local
649 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm646x_init_time()
650 dm646x_pll1_init(NULL, pll1, NULL); in dm646x_init_time()

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