Lines Matching refs:pll1
37 u32 pll1; member
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
205 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
223 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
237 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
268 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
286 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
305 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
324 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
347 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
365 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
384 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
403 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
869 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()