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/Linux-v4.19/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi49 pll0: pll0@800 { label
54 clock-output-names = "pll0", "pll0-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dqoriq-clockgen2.dtsi48 pll0: pll0@800 { label
53 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
Dt1040si-post.dtsi433 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
435 clock-names = "pll0", "pll0-div2", "pll1-div4",
444 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
446 clock-names = "pll0", "pll0-div2", "pll1-div4",
455 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
457 clock-names = "pll0", "pll0-div2", "pll1-div4",
466 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
Dt2081si-post.dtsi543 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
545 clock-names = "pll0", "pll0-div2", "pll0-div4",
554 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
556 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4si-post.dtsi409 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
411 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dt4240si-post.dtsi982 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
985 clock-names = "pll0", "pll0-div2", "pll0-div4",
995 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
998 clock-names = "pll0", "pll0-div2", "pll0-div4",
/Linux-v4.19/drivers/bcma/
Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
349 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
354 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
366 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt152 pll0: pll0@800 {
157 clock-output-names = "pll0", "pll0-div2";
172 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
173 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
182 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
Drenesas,rcar-gen2-cpg-clocks.txt24 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
45 clock-output-names = "main", "pll0, "pll1", "pll3",
Dimx28-clock.txt15 pll0 1
/Linux-v4.19/arch/arm/boot/dts/
Dstih407-clock.dtsi80 compatible = "st,clkgen-pll0";
119 clk_s_c0_pll0: clk-s-c0-pll0 {
121 compatible = "st,clkgen-pll0";
125 clock-output-names = "clk-s-c0-pll0-odf-0";
126 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
Dstih410-clock.dtsi80 compatible = "st,clkgen-pll0";
120 clk_s_c0_pll0: clk-s-c0-pll0 {
122 compatible = "st,clkgen-pll0";
126 clock-output-names = "clk-s-c0-pll0-odf-0";
127 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
Dstih418-clock.dtsi81 compatible = "st,clkgen-pll0";
118 clk_s_c0_pll0: clk-s-c0-pll0 {
120 compatible = "st,clkgen-pll0";
124 clock-output-names = "clk-s-c0-pll0-odf-0";
/Linux-v4.19/arch/arc/boot/dts/
Dabilis_tb10x.dtsi60 pll0: oscillator { label
63 clock-output-names = "pll0";
68 clocks = <&pll0>;
74 clocks = <&pll0>;
/Linux-v4.19/drivers/gpu/drm/tegra/
Dhdmi.c36 u32 pll0; member
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
202 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
220 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
234 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
248 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
266 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
284 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
303 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
322 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
Dsor.c292 unsigned int pll0; member
1155 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1157 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1701 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1724 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
2244 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2247 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt12 "st,clkgen-pll0"

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