292 	unsigned int pll0;  member
1155 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_power_down()
1157 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_power_down()
1661 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1701 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1703 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1724 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
1727 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_edp_enable()
2244 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2247 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2424 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2431 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);  in tegra_sor_hdmi_enable()
2793 	.pll0 = 0x17,
2818 	.pll0 = 0x17,
2862 	.pll0 = 0x163,