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/Linux-v4.19/drivers/gpu/drm/xen/
Dxen_drm_front_kms.c97 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
99 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
104 if (pipeline->pending_event) in send_pending_event()
105 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
106 pipeline->pending_event = NULL; in send_pending_event()
114 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
123 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
130 pipeline->conn_connected = false; in display_enable()
138 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
143 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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Dxen_drm_front_conn.c47 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
51 pipeline->conn_connected = false; in connector_detect()
53 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
61 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
72 videomode.hactive = pipeline->width; in connector_get_modes()
73 videomode.vactive = pipeline->height; in connector_get_modes()
103 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
108 pipeline->conn_connected = true; in xen_drm_front_conn_init()
Dxen_drm_front.h124 struct xen_drm_front_drm_pipeline pipeline[XEN_DRM_FRONT_MAX_CRTCS]; member
137 int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline,
Dxen_drm_front_kms.h23 void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline,
/Linux-v4.19/drivers/isdn/mISDN/
Ddsp_pipeline.c194 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
196 if (!pipeline) in dsp_pipeline_init()
199 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
208 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
212 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
215 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
216 pipeline)); in _dsp_pipeline_destroy()
223 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
226 if (!pipeline) in dsp_pipeline_destroy()
229 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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Ddsp.h236 pipeline; member
271 extern int dsp_pipeline_init(struct dsp_pipeline *pipeline);
272 extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline);
273 extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg);
274 extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data,
276 extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data,
/Linux-v4.19/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_crtc.c99 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
106 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
131 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
134 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
145 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
163 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
222 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
228 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
230 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
364 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
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Dmdp5_ctl.c143 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in set_ctl_op() argument
146 struct mdp5_interface *intf = pipeline->intf; in set_ctl_op()
167 if (pipeline->r_mixer) in set_ctl_op()
176 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) in mdp5_ctl_set_pipeline() argument
179 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_pipeline()
185 set_ctl_op(ctl, pipeline); in mdp5_ctl_set_pipeline()
191 struct mdp5_pipeline *pipeline) in start_signal_needed() argument
193 struct mdp5_interface *intf = pipeline->intf; in start_signal_needed()
233 struct mdp5_pipeline *pipeline, in mdp5_ctl_set_encoder_state() argument
236 struct mdp5_interface *intf = pipeline->intf; in mdp5_ctl_set_encoder_state()
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Dmdp5_cmd_encoder.c154 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
161 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
162 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
174 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
183 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
185 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
Dmdp5_ctl.h45 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
63 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
80 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
Dmdp5_encoder.c217 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_disable() local
226 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_vid_encoder_disable()
231 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_disable()
254 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_vid_encoder_enable() local
265 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_vid_encoder_enable()
267 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_vid_encoder_enable()
321 mdp5_cstate->pipeline.intf = intf; in mdp5_encoder_atomic_check()
/Linux-v4.19/drivers/net/wireless/ti/wl18xx/
Ddebugfs.c157 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
158 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
159 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
160 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
161 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
162 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
163 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
164 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
165 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
166 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/Linux-v4.19/tools/testing/selftests/kvm/lib/
Dassert.c34 const char *pipeline = "|cat -n 1>&2"; in test_dump_stack() local
35 char cmd[strlen(addr2line) + strlen(pipeline) + in test_dump_stack()
52 c += sprintf(c, "%s", pipeline); in test_dump_stack()
/Linux-v4.19/Documentation/devicetree/bindings/display/
Dsimple-framebuffer-sunxi.txt8 on which pipeline is being used. As such they are solely intended for
13 - allwinner,pipeline, one of:
32 allwinner,pipeline = "de_be0-lcd0-hdmi";
/Linux-v4.19/Documentation/media/v4l-drivers/
Dqcom_camss.rst36 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
38 interface feeds the input data to the image processing pipeline. The image
39 processing pipeline contains also a scale and crop module at the end. Three
41 pipeline. The VFE also contains the AXI bus interface which writes the output
135 The media controller pipeline graph is as follows (with connected two / three
144 Media pipeline graph 8x16
150 Media pipeline graph 8x96
Dfimc.rst29 - dynamic pipeline re-configuration at runtime (re-attachment of any FIMC
107 In order to enable more precise camera pipeline control through the sub-device
111 In typical use case there could be a following capture pipeline configuration:
118 devices belonging to the pipeline is done at the video node driver.
/Linux-v4.19/Documentation/media/uapi/v4l/
Ddev-subdev.rst90 responsible for configuring every block in the video pipeline according
91 to the requested format at the pipeline input and/or output.
94 image sizes at the output of a pipeline can be achieved using different
96 :ref:`pipeline-scaling`, where image scaling can be performed on both
102 .. kernel-figure:: pipeline.dot
103 :alt: pipeline.dot
108 High quality and high speed pipeline configuration
114 Depending on the use case (quality vs. speed), the pipeline must be
116 every point in the pipeline explicitly.
126 whole pipeline and making sure that connected pads have compatible
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/Linux-v4.19/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,video.txt7 Xilinx video IP pipeline processes video streams through one or more Xilinx
10 node of the VIPP represents as a top level node of the pipeline and defines
Dvideo.txt6 creating a video pipeline.
12 The whole pipeline is represented by an AMBA bus child node in the device
/Linux-v4.19/Documentation/media/kapi/
Dmc-core.rst22 in a System-on-Chip image processing pipeline), DMA channels or physical
207 When starting streaming, drivers must notify all entities in the pipeline to
215 the pipe argument will be stored in every entity in the pipeline.
217 in higher-level pipeline structures and can then access the
218 pipeline through the struct :c:type:`media_entity`
222 The pipeline pointer must be identical for all nested calls to the function.
249 for any entity which has sink pads in the pipeline. The
/Linux-v4.19/drivers/gpu/drm/sun4i/
Dsun4i_drv.c377 struct device_node *pipeline = of_parse_phandle(np, in sun4i_drv_probe() local
380 if (!pipeline) in sun4i_drv_probe()
383 kfifo_put(&list.fifo, pipeline); in sun4i_drv_probe()
/Linux-v4.19/Documentation/media/
D.gitignore3 uapi/v4l/pipeline.svg
/Linux-v4.19/Documentation/devicetree/bindings/display/bridge/
Dmegachips-stdpxxxx-ge-b850v3-fw.txt5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the
/Linux-v4.19/Documentation/devicetree/bindings/arc/
Darchs-pct.txt3 The ARC HS can be configured with a pipeline performance monitor for counting
Dpct.txt3 The ARC700 can be configured with a pipeline performance monitor for counting

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