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Searched refs:pipe_bpp (Results 1 – 15 of 15) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dvlv_dsi_pll.c255 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp) in assert_bpp_mismatch() argument
259 WARN(bpp != pipe_bpp, in assert_bpp_mismatch()
261 bpp, pipe_bpp); in assert_bpp_mismatch()
264 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, in vlv_dsi_get_pclk() argument
323 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in vlv_dsi_get_pclk()
325 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_dsi_get_pclk()
330 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, in bxt_dsi_get_pclk() argument
340 if (!pipe_bpp) { in bxt_dsi_get_pclk()
352 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in bxt_dsi_get_pclk()
354 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_dsi_get_pclk()
Dintel_dsi.h142 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
152 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
Dintel_lvds.c296 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
415 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
417 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
418 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
Dintel_ddi.c1440 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1692 switch (crtc_state->pipe_bpp) { in intel_ddi_set_pipe_settings()
1706 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_pipe_settings()
1743 switch (crtc_state->pipe_bpp) { in intel_ddi_enable_transcoder_func()
3168 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
3171 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
3174 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
3177 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
3227 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
3242 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_ddi_get_config()
[all …]
Dintel_hdmi.c627 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
632 switch (pipe_bpp) { in gcp_default_phase_possible()
683 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_set_gcp_infoframe()
1156 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
1310 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
1356 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
1368 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
1608 if (crtc_state->pipe_bpp <= 8*3) in hdmi_deep_color_possible()
1778 pipe_config->pipe_bpp = desired_bpp; in intel_hdmi_compute_config()
Dvlv_dsi.c1121 pipe_config->pipe_bpp = in bxt_dsi_get_pipe_config()
1124 bpp = pipe_config->pipe_bpp; in bxt_dsi_get_pipe_config()
1262 pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp, in intel_dsi_get_config()
1265 pclk = vlv_dsi_get_pclk(encoder, pipe_config->pipe_bpp, in intel_dsi_get_config()
Dintel_crt.c395 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
400 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
Dintel_dp.c1669 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1748 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1813 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
1817 pipe_config->pipe_bpp), in intel_dp_compute_link_config()
1891 pipe_config->pipe_bpp != 18 && in intel_dp_compute_config()
1899 intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count, in intel_dp_compute_config()
1908 intel_link_compute_m_n(pipe_config->pipe_bpp, in intel_dp_compute_config()
2765 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_dp_get_config()
2780 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_dp_get_config()
2781 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
Dintel_display.c6464 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6468 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6472 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6473 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6475 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6500 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
7436 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
7440 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
7851 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
7854 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
[all …]
Dintel_dp_mst.c69 pipe_config->pipe_bpp = bpp; in intel_dp_mst_compute_config()
Dintel_tv.c890 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
Dintel_drv.h817 int pipe_bpp; member
Dintel_panel.c370 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
Dintel_sdvo.c1134 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
Di915_debugfs.c3202 yesno(pipe_config->dither), pipe_config->pipe_bpp); in i915_display_info()