Searched refs:performance_level_count (Results 1 – 13 of 13) sorted by relevance
807 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()826 ps->performance_levels[ps->performance_level_count - 1].vddci; in ni_apply_state_adjust_rules()833 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()844 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()850 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()855 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()863 for (i = 1; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()868 for (i = 0; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()872 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()[all …]
2307 if (state->performance_level_count == 0) in si_populate_power_containment_values()2310 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()2321 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()2389 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()2392 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()2413 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()3028 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()3033 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()3053 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()3079 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()[all …]
173 u16 performance_level_count; member
46 u16 performance_level_count; member
828 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()839 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()3754 if (state->performance_level_count < 1) in ci_trim_dpm_states()3757 if (state->performance_level_count == 1) in ci_trim_dpm_states()3859 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()3861 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()3900 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()3901 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()4802 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()5478 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()[all …]
2405 if (state->performance_level_count == 0) in si_populate_power_containment_values()2408 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()2419 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()2486 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()2489 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()2510 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()3181 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()3182 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()3199 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()3200 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()[all …]
47 u16 performance_level_count; member
960 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()971 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()3901 if (state->performance_level_count < 1) in ci_trim_dpm_states()3904 if (state->performance_level_count == 1) in ci_trim_dpm_states()4008 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()4010 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()4046 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()4047 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()4953 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()5587 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()[all …]
615 u16 performance_level_count; member
2901 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, in smu7_apply_state_adjust_rules()2911 for (i = 0; i < smu7_ps->performance_level_count; i++) { in smu7_apply_state_adjust_rules()2963 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()2997 for (i = 0; i < smu7_ps->performance_level_count; i++) { in smu7_apply_state_adjust_rules()3027 [smu7_ps->performance_level_count-1].memory_clock; in smu7_dpm_get_mclk()3049 [smu7_ps->performance_level_count-1].engine_clock; in smu7_dpm_get_sclk()3163 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()3166 …(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHIC… in smu7_get_pp_table_entry_callback_func_v1()3171 (smu7_power_state->performance_level_count <= in smu7_get_pp_table_entry_callback_func_v1()3191 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()[all …]
3022 [vega10_power_state->performance_level_count++]); in vega10_get_pp_table_entry_callback_func()3025 (vega10_power_state->performance_level_count < in vega10_get_pp_table_entry_callback_func()3031 (vega10_power_state->performance_level_count <= in vega10_get_pp_table_entry_callback_func()3046 [vega10_power_state->performance_level_count++]); in vega10_get_pp_table_entry_callback_func()3122 if (vega10_ps->performance_level_count != 2) in vega10_apply_state_adjust_rules()3131 for (i = 0; i < vega10_ps->performance_level_count; i++) { in vega10_apply_state_adjust_rules()3238 for (i = 0; i < vega10_ps->performance_level_count; i++) { in vega10_apply_state_adjust_rules()3343 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), in vega10_trim_dpm_states()3347 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; in vega10_trim_dpm_states()3620 [vega10_ps->performance_level_count - 1].gfx_clock; in vega10_dpm_get_sclk()[all …]
82 uint16_t performance_level_count; member
109 uint16_t performance_level_count; member
