2307 	if (state->performance_level_count == 0)  in si_populate_power_containment_values()
2310 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_power_containment_values()
2321 	for (i = 1; i < state->performance_level_count; i++) {  in si_populate_power_containment_values()
2389 	if (state->performance_level_count == 0)  in si_populate_sq_ramping_values()
2392 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_sq_ramping_values()
2413 	for (i = 0; i < state->performance_level_count; i++) {  in si_populate_sq_ramping_values()
3028 	for (i = ps->performance_level_count - 2; i >= 0; i--) {  in si_apply_state_adjust_rules()
3033 		for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3053 	for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3079 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in si_apply_state_adjust_rules()
3080 		vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;  in si_apply_state_adjust_rules()
3087 		sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;  in si_apply_state_adjust_rules()
3088 		vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;  in si_apply_state_adjust_rules()
3109 		for (i = 1; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3113 		for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3118 		for (i = 1; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3128 		for (i = 1; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3132 		for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3137 		for (i = 1; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3145 	for (i = 0; i < ps->performance_level_count; i++)  in si_apply_state_adjust_rules()
3149 	for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3166 	for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3174 	for (i = 0; i < ps->performance_level_count; i++) {  in si_apply_state_adjust_rules()
3403 	u32 levels = ps->performance_level_count;  in si_dpm_force_performance_level()
4325 	for (i = 0; i < state->performance_level_count; i++) {  in si_do_program_memory_timing_parameters()
4967 	for (i = 0; i < ps->performance_level_count - 1; i++)  in si_populate_smc_sp()
4970 	smc_state->levels[ps->performance_level_count - 1].bSP =  in si_populate_smc_sp()
5094 	if (state->performance_level_count >= 9)  in si_populate_smc_t()
5097 	if (state->performance_level_count < 2) {  in si_populate_smc_t()
5105 	for (i = 0; i <= state->performance_level_count - 2; i++) {  in si_populate_smc_t()
5123 		high_bsp = (i == state->performance_level_count - 2) ?  in si_populate_smc_t()
5198 	if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)  in si_convert_power_state_to_smc()
5201 	threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;  in si_convert_power_state_to_smc()
5215 	for (i = 0; i < state->performance_level_count; i++) {  in si_convert_power_state_to_smc()
5275 		((new_state->performance_level_count - 1) *  in si_upload_sw_state()
5641 	for (i = 0; i < state->performance_level_count; i++) {  in si_convert_mc_reg_table_to_smc()
5703 				    sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,  in si_upload_mc_reg_table()
5723 	for (i = 0; i < state->performance_level_count; i++) {  in si_get_maximum_link_speed()
6739 	ps->performance_level_count = index + 1;  in si_parse_pplib_clock_info()
7097 	if (current_index >= ps->performance_level_count) {  in si_dpm_debugfs_print_current_performance_level()
7117 	if (current_index >= ps->performance_level_count) {  in si_dpm_get_current_sclk()
7135 	if (current_index >= ps->performance_level_count) {  in si_dpm_get_current_mclk()