Searched refs:mr32 (Results 1 – 4 of 4) sorted by relevance
36 reg = mr32(MVS_GBL_PORT_TYPE); in mvs_64xx_detect_porttype()49 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()95 reg = mr32(MVS_PHY_CTL); in mvs_64xx_stp_reset()145 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()151 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()168 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()187 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()200 if (!(mr32(MVS_GBL_CTL) & HBA_RST)) in mvs_64xx_chip_reset()203 if (mr32(MVS_GBL_CTL) & HBA_RST) { in mvs_64xx_chip_reset()226 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_phy_disable()[all …]
30 #define mr32(reg) readl(regs + reg) macro34 mr32(reg); \48 return mr32(MVS_CMD_DATA); in mvs_cr32()61 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) : in mvs_read_phy_ctl()62 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4); in mvs_read_phy_ctl()191 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_int_sata()203 stat = mr32(MVS_INT_STAT); in mvs_int_full()230 return mr32(MVS_RX_CONS_IDX); in mvs_rx_update()
265 tmp = mr32(MVS_PCS); in mvs_94xx_enable_xmt()338 tmp = mr32(MVS_HST_CHIP_CONFIG); in mvs_94xx_sgpio_init()388 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()396 cctl = mr32(MVS_CTL) & 0xFFFF; in mvs_94xx_init()403 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()457 tmp = mr32(MVS_PA_VSR_PORT); in mvs_94xx_init()518 cctl = mr32(MVS_CTL); in mvs_94xx_init()525 tmp = mr32(MVS_PCS); in mvs_94xx_init()613 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_enable()628 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_disable()[all …]
340 (((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \341 mr32(MVS_STP_REG_SET_0))
