36 	reg = mr32(MVS_GBL_PORT_TYPE);  in mvs_64xx_detect_porttype()
49 	tmp = mr32(MVS_PCS);  in mvs_64xx_enable_xmt()
95 		reg = mr32(MVS_PHY_CTL);  in mvs_64xx_stp_reset()
145 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
151 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
168 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
187 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
200 		if (!(mr32(MVS_GBL_CTL) & HBA_RST))  in mvs_64xx_chip_reset()
203 	if (mr32(MVS_GBL_CTL) & HBA_RST) {  in mvs_64xx_chip_reset()
226 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_disable()
248 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_enable()
268 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
276 	cctl = mr32(MVS_CTL) & 0xFFFF;  in mvs_64xx_init()
299 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
378 	cctl = mr32(MVS_CTL);  in mvs_64xx_init()
386 	tmp = mr32(MVS_PCS);  in mvs_64xx_init()
441 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_enable()
450 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_disable()
460 		stat = mr32(MVS_GBL_INT_STAT);  in mvs_64xx_isr_status()
503 		tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);  in mvs_64xx_issue_stop()
507 	tmp = mr32(MVS_PCS) | 0xFF00;  in mvs_64xx_issue_stop()
521 		tmp = mr32(MVS_PCS);  in mvs_64xx_free_reg_set()
524 		tmp = mr32(MVS_CTL);  in mvs_64xx_free_reg_set()
528 	tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);  in mvs_64xx_free_reg_set()
545 	tmp = mr32(MVS_PCS);  in mvs_64xx_assign_reg_set()
549 			tmp = mr32(MVS_CTL);  in mvs_64xx_assign_reg_set()
558 			tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);  in mvs_64xx_assign_reg_set()
663 	tmp = mr32(MVS_PCS);  in mvs_64xx_clear_active_cmds()
666 	tmp = mr32(MVS_CTL);  in mvs_64xx_clear_active_cmds()