Searched refs:intf_cfg (Results 1 – 4 of 4) sorted by relevance
444 u32 intf_cfg = 0; in dpu_hw_ctl_intf_cfg() local446 intf_cfg |= (cfg->intf & 0xF) << 4; in dpu_hw_ctl_intf_cfg()449 intf_cfg |= BIT(19); in dpu_hw_ctl_intf_cfg()450 intf_cfg |= (cfg->mode_3d - 0x1) << 20; in dpu_hw_ctl_intf_cfg()455 intf_cfg &= ~BIT(17); in dpu_hw_ctl_intf_cfg()456 intf_cfg &= ~(0x3 << 15); in dpu_hw_ctl_intf_cfg()459 intf_cfg |= BIT(17); in dpu_hw_ctl_intf_cfg()460 intf_cfg |= ((cfg->stream_sel & 0x3) << 15); in dpu_hw_ctl_intf_cfg()467 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
106 u32 intf_cfg; in dpu_hw_intf_setup_timing_engine() local109 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()146 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ in dpu_hw_intf_setup_timing_engine()152 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ in dpu_hw_intf_setup_timing_engine()196 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
75 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in _dpu_encoder_phys_cmd_update_intf_cfg() local84 intf_cfg.intf = phys_enc->intf_idx; in _dpu_encoder_phys_cmd_update_intf_cfg()85 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; in _dpu_encoder_phys_cmd_update_intf_cfg()86 intf_cfg.stream_sel = cmd_enc->stream_sel; in _dpu_encoder_phys_cmd_update_intf_cfg()87 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()88 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
251 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_phys_vid_setup_timing_engine() local286 intf_cfg.intf = vid_enc->hw_intf->idx; in dpu_encoder_phys_vid_setup_timing_engine()287 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; in dpu_encoder_phys_vid_setup_timing_engine()288 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_phys_vid_setup_timing_engine()289 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()294 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
