Searched refs:interconnect (Results 1 – 25 of 52) sorted by relevance
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1 Texas Instruments sysc interconnect target module wrapper binding3 Texas Instruments SoCs can have a generic interconnect target module5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc8 of the interconnect.10 Each interconnect target module can have one or more devices connected to11 it. There is a set of control registers for managing interconnect target12 module clocks, idle modes and interconnect level resets for the module.15 space of the first child device IP block managed by the interconnect41 - reg shall have register areas implemented for the interconnect45 interconnect target module in question such as[all …]
1 L4 interconnect bindings3 These bindings describe the OMAP SoCs L4 interconnect bus.19 - reg : registers link agent and interconnect agent and access protection21 interconnect agent instances, "ap" for access if it exists25 l4: interconnect@48000000 {
2 ARM CCI cache coherent interconnect binding description6 cache coherent interconnect (CCI) that is capable of monitoring bus14 * CCI interconnect node20 through the CCI interconnect is the same as the one seen from the51 CCI interconnect node can define the following child nodes:56 Parent node must be CCI interconnect node.85 Parent node must be CCI interconnect node.124 * CCI interconnect bus masters129 A CCI interconnect bus master node must contain the following
24 the interconnect should be "apb_pclk" and the clock is
47 cbass_main: interconnect@100000 {64 cbass_mcu: interconnect@28380000 {75 cbass_wakeup: interconnect@42040000 {
4 interconnect target module. The clkctrl clock controller manages functional8 interconnect target module on omap4 and later variants.
21 interconnect for ARM platforms.73 Driver to enable OMAP interconnect error handling driver.144 bool "TI sysc interconnect target module driver"147 Generic driver for Texas Instruments interconnect target module
7 <L3 interconnect address, size>;
10 <L3 interconnect address, size>;
22 /* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
124 * XXX: Use a flat representation of the OMAP4 interconnect.125 * The real OMAP interconnect network is quite complex.142 l4_wkup: interconnect@4a300000 {145 l4_cfg: interconnect@4a000000 {148 l4_per: interconnect@48000000 {
95 /* Only some L4 CFG interconnect ranges are different on 4460 */
22 ti,hwmods: Shall contain the TI interconnect module name if needed
10 - clock-names : should be "ic" for interconnect clock and "clk48"
12 - clock-names : should be "ic" for interconnect clock and "clk48"
66 u8 interconnect; member
3 UCTL is the bridge unit between the I/O interconnect (an internal bus)
13 within the SoC. It is added as a child node of the parent interconnect bus
10 RapidIO is a high speed switched fabric interconnect with features aimed
8 that is optimized for die-level interconnect between an Application Processor
22 connected together with some sort of system interconnect--e.g., a crossbar or30 is handled in hardware by the processor caches and/or the system interconnect.98 "local" to the underlying physical resources and off the system interconnect--
4 CCN-504 is a ring-bus interconnect consisting of 11 crosspoints
44 - ti,hwmods: Shall contain TI interconnect module name if needed
41 interconnect.
