/Linux-v4.19/tools/perf/Documentation/ |
D | itrace.txt | 1 i synthesize instructions events 16 In addition, the period (default 100000) for instructions events 19 i instructions 25 Also the call chain size (default 16, max. 1024) for instructions or 29 instructions or transactions events can be specified. 31 It is also possible to skip events generated (instructions, branches, transactions, 36 skips the first million instructions.
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/Linux-v4.19/Documentation/arm64/ |
D | legacy_instructions.txt | 2 emulation of instructions which have been deprecated, or obsoleted in 13 Generates undefined instruction abort. Default for instructions that 21 instructions, .e.g., CP15 barriers 27 instructions. Using hardware execution generally provides better 29 about the use of the deprecated instructions. 32 architecture. Deprecated instructions should default to emulation 33 while obsolete instructions must be undefined by default. 38 Supported legacy instructions
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/Linux-v4.19/drivers/watchdog/ |
D | wdat_wdt.c | 50 struct list_head *instructions[MAX_WDAT_ACTIONS]; member 115 if (action >= ARRAY_SIZE(wdat->instructions)) in wdat_wdt_run_action() 118 if (!wdat->instructions[action]) in wdat_wdt_run_action() 124 list_for_each_entry(instr, wdat->instructions[action], node) { in wdat_wdt_run_action() 372 struct list_head *instructions; in wdat_wdt_probe() local 420 instructions = wdat->instructions[action]; in wdat_wdt_probe() 421 if (!instructions) { in wdat_wdt_probe() 422 instructions = devm_kzalloc(&pdev->dev, in wdat_wdt_probe() 423 sizeof(*instructions), GFP_KERNEL); in wdat_wdt_probe() 424 if (!instructions) in wdat_wdt_probe() [all …]
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/Linux-v4.19/Documentation/arm/ |
D | swp_emulation | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds 5 moving to the load-locked/store-conditional instructions LDREX and STREX. 8 instructions, triggering an undefined instruction exception when executed. 9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
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D | kernel_mode_neon.txt | 6 * Use only NEON instructions, or VFP instructions that don't rely on support 18 It is possible to use NEON instructions (and in some cases, VFP instructions) in 23 may call schedule()], as NEON or VFP instructions will be executed in a 42 should be called before any kernel mode NEON or VFP instructions are issued. 73 Such software assistance is currently not implemented for VFP instructions 81 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions 83 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the 85 instructions appearing in unexpected places if no special care is taken. 96 both NEON and VFP instructions will only ever appear in designated compilation
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/Linux-v4.19/tools/testing/selftests/powerpc/pmu/ |
D | count_instructions.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument 38 thirty_two_instruction_loop(instructions >> 5); in do_count_loop() 45 expected = instructions + overhead; in do_count_loop() 53 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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/Linux-v4.19/Documentation/bpf/ |
D | bpf_design_QA.rst | 89 the program terminates in less than 4096 instructions. 94 Q: LD_ABS and LD_IND instructions vs C code 104 Q: BPF instructions mapping not one-to-one to native CPU 106 Q: It seems not all BPF instructions are one-to-one to native CPU. 129 of LD_ABS insn). Those instructions need to invoke epilogue and 132 Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning? 136 due to lack of these compare instructions and they were added. 137 These two instructions is a perfect example what kind of new BPF 138 instructions are acceptable and can be added in the future. 139 These two already had equivalent instructions in native CPUs. [all …]
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/Linux-v4.19/tools/testing/selftests/powerpc/pmu/ebb/ |
D | instruction_count_test.c | 25 static int do_count_loop(struct event *event, uint64_t instructions, in do_count_loop() argument 37 thirty_two_instruction_loop(instructions >> 5); in do_count_loop() 46 expected = instructions + overhead; in do_count_loop() 51 printf("Looped for %lu instructions, overhead %lu\n", instructions, overhead); in do_count_loop()
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/Linux-v4.19/tools/memory-model/ |
D | linux-kernel.bell | 20 instructions R[{'once,'acquire,'noreturn}] 21 instructions W[{'once,'release}] 22 instructions RMW[{'once,'acquire,'release}] 33 instructions F[Barriers]
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/Linux-v4.19/Documentation/virtual/kvm/ |
D | ppc-pv.txt | 6 instructions and can emulate them accordingly. 9 instructions that needlessly return us to the hypervisor even though they 12 This is what the PPC PV interface helps with. It takes privileged instructions 32 'hypercall-instructions'. This property contains at most 4 opcodes that make 33 up the hypercall. To call a hypercall, just call these instructions. 129 Patched instructions 132 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions 138 also act on the shared page. So calling privileged instructions still works as 178 Some instructions require more logic to determine what's going on than a load 180 RAM around where we can live translate instructions to. What happens is the
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/Linux-v4.19/arch/arm/crypto/ |
D | Kconfig | 8 implemented using ARM specific CPU features or instructions. 28 using optimized ARM NEON assembly, when NEON instructions are 73 tristate "Bit sliced AES using NEON instructions" 109 tristate "CRCT10DIF digest algorithm using PMULL instructions" 114 tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
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/Linux-v4.19/Documentation/virtual/ |
D | paravirt_ops.txt | 13 corresponding to low level critical instructions and high level 25 Usually these operations correspond to low level critical instructions. They 31 because they include sensitive instructions or some of code paths in
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/Linux-v4.19/arch/arm64/crypto/ |
D | Kconfig | 8 implemented using ARM64 specific CPU features or instructions. 65 tristate "CRCT10DIF digest algorithm using PMULL instructions" 75 tristate "AES core cipher using scalar instructions" 101 tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
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/Linux-v4.19/tools/perf/tests/attr/ |
D | README | 50 perf record --group -e cycles,instructions kill (test-record-group) 51 perf record -e '{cycles,instructions}' kill (test-record-group1) 62 perf stat --group -e cycles,instructions kill (test-stat-group) 63 perf stat -e '{cycles,instructions}' kill (test-stat-group1)
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D | test-stat-group1 | 3 args = -e '{cycles,instructions}' kill >/dev/null 2>&1
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D | test-stat-group | 3 args = --group -e cycles,instructions kill >/dev/null 2>&1
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/Linux-v4.19/arch/nios2/platform/ |
D | Kconfig.platform | 53 comment "Nios II instructions" 85 bool "Enable BMX instructions" 90 the BMX Bit Manipulation Extension instructions. Enables 94 bool "Enable CDX instructions" 99 the CDX Bit Manipulation Extension instructions. Enables
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/Linux-v4.19/drivers/media/pci/tw68/ |
D | tw68-risc.c | 146 u32 instructions, fields; in tw68_risc_buffer() local 160 instructions = fields * (1 + (((bpl + padding) * lines) / in tw68_risc_buffer() 162 buf->size = instructions * 8; in tw68_risc_buffer()
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/Linux-v4.19/Documentation/arm/nwfpe/ |
D | README.FPE | 5 instructions. It follows the conventions in the ARM manual. 22 These instructions are fully implemented. 34 These instructions are fully implemented. They store/load three words 43 Conversions, read/write status/control register instructions 56 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and 60 Compare instructions 89 equivalent to the MUF/DVF/RDV instructions. This is acceptable according
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/Linux-v4.19/arch/m68k/ifpsp060/ |
D | fplsp.doc | 36 FP instructions not implemented in 68060 hardware. These 37 instructions normally take exception vector #11 40 By re-compiling a program that uses these instructions, and 42 instructions, a program can avoid the overhead associated 110 this exception using implemented floating-point instructions. 120 The package does not attempt to correctly emulate instructions 126 subroutine calls for all fp instructions. The code does NOT emulate
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/Linux-v4.19/drivers/acpi/apei/ |
D | apei-internal.h | 33 u32 instructions; member 40 u32 instructions,
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/Linux-v4.19/arch/arm64/ |
D | Kconfig | 324 The workaround promotes data cache clean instructions to 333 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th… 345 The workaround promotes data cache clean instructions to 367 The workaround promotes data cache clean instructions to 376 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 388 The workaround promotes data cache clean instructions to 404 instructions to Write-Back memory are mixed with Device loads. 462 enables PLT support to replace certain ADRP instructions, which can 519 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 523 instructions may cause the icache to become corrupted if it [all …]
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/Linux-v4.19/Documentation/ |
D | lzo.txt | 20 The stream is composed of a series of instructions, operands, and data. The 21 instructions consist in a few bits representing an opcode, and bits forming 29 as a piece of information for next instructions. 55 ranges, resulting in multiple copy instructions using different encodings. 74 In the code some length checks are missing because certain instructions 76 because it has already been guaranteed before parsing the instructions.
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/Linux-v4.19/drivers/media/pci/cx88/ |
D | cx88-core.c | 144 u32 instructions, fields; in cx88_risc_buffer() local 159 instructions = fields * (1 + ((bpl + padding) * lines) / in cx88_risc_buffer() 161 instructions += 4; in cx88_risc_buffer() 162 risc->size = instructions * 8; in cx88_risc_buffer() 189 u32 instructions; in cx88_risc_databuffer() local 198 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; in cx88_risc_databuffer() 199 instructions += 3; in cx88_risc_databuffer() 200 risc->size = instructions * 8; in cx88_risc_databuffer()
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/Linux-v4.19/arch/ia64/ |
D | Kconfig.debug | 45 compare-and-exchange instructions. This is slow! Itaniums 54 and restore instructions. It's useful for tracking down spinlock
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