Lines Matching refs:instructions

324 	  The workaround promotes data cache clean instructions to
333 	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
345 	  The workaround promotes data cache clean instructions to
367 	  The workaround promotes data cache clean instructions to
376 	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
388 	  The workaround promotes data cache clean instructions to
404 	  instructions to Write-Back memory are mixed with Device loads.
462 	  enables PLT support to replace certain ADRP instructions, which can
519 	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
523 	  instructions may cause the icache to become corrupted if it
594 	  Falkor CPU may speculatively fetch instructions from an improper
947 	bool "Emulate deprecated/obsolete ARMv8 instructions"
951 	  Legacy software support may require certain instructions
962 	bool "Emulate SWP/SWPB instructions"
964 	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
966 	  emulation of these instructions for userspace using LDXR/STXR.
983 	bool "Emulate CP15 Barrier instructions"
985 	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
988 	  instructions instead.
991 	  instructions for AArch32 userspace code. When this option is
1056 	bool "Atomic instructions"
1060 	  atomic instructions that are designed specifically to scale in
1063 	  Say Y here to make use of these instructions for the in-kernel
1065 	  not support these instructions and requires the kernel to be
1066 	  built with binutils >= 2.25 in order for the new instructions
1091 	  causes the 'unprivileged' variant of the load/store instructions to
1095 	  variant of the load/store instructions. This ensures that user-space
1104 	  regular load/store instructions if the cpu does not implement the