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Searched refs:infracfg (Results 1 – 22 of 22) sorted by relevance

/Linux-v4.19/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,infracfg.txt1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt8135-infracfg", "syscon"
15 - "mediatek,mt8173-infracfg", "syscon"
19 The infracfg controller uses the common clk binding from
29 infracfg: power-controller@10001000 {
[all …]
/Linux-v4.19/drivers/soc/mediatek/
Dmtk-infracfg.c40 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
47 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
50 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
52 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
71 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
78 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
80 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
82 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
DMakefile1 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
Dmtk-scpsys.c150 struct regmap *infracfg; member
258 ret = mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_power_on()
292 ret = mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_power_off()
391 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
393 if (IS_ERR(scp->infracfg)) { in init_scp()
395 PTR_ERR(scp->infracfg)); in init_scp()
396 return ERR_CAST(scp->infracfg); in init_scp()
/Linux-v4.19/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt29 - infracfg: must contain a phandle to the infracfg controller
58 infracfg = <&infracfg>;
Dpwrap.txt55 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
/Linux-v4.19/include/linux/soc/mediatek/
Dinfracfg.h35 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
37 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
/Linux-v4.19/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
209 clocks = <&infracfg CLK_INFRA_CA57SEL>,
221 clocks = <&infracfg CLK_INFRA_CA57SEL>,
/Linux-v4.19/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
193 infracfg: infracfg@10000000 { label
194 compatible = "mediatek,mt7622-infracfg",
205 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
207 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
230 infracfg = <&infracfg>;
239 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
284 clocks = <&infracfg CLK_INFRA_TRNG>;
549 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
Dmt8173.dtsi159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
172 clocks = <&infracfg CLK_INFRA_CA53SEL>,
185 clocks = <&infracfg CLK_INFRA_CA57SEL>,
198 clocks = <&infracfg CLK_INFRA_CA57SEL>,
327 infracfg: power-controller@10001000 { label
328 compatible = "mediatek,mt8173-infracfg", "syscon";
427 infracfg = <&infracfg>;
441 clocks = <&infracfg CLK_INFRA_CLK_13M>,
450 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
452 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
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Dmt2712e.dtsi250 infracfg: syscon@10001000 { label
251 compatible = "mediatek,mt2712-infracfg", "syscon";
291 infracfg = <&infracfg>;
Dmt6797.dtsi127 compatible = "mediatek,mt6797-infracfg", "syscon";
140 infracfg = <&infrasys>;
/Linux-v4.19/arch/arm/boot/dts/
Dmt7623.dtsi79 clocks = <&infracfg CLK_INFRA_CPUSEL>,
91 clocks = <&infracfg CLK_INFRA_CPUSEL>,
103 clocks = <&infracfg CLK_INFRA_CPUSEL>,
115 clocks = <&infracfg CLK_INFRA_CPUSEL>,
215 infracfg: syscon@10001000 { label
216 compatible = "mediatek,mt7623-infracfg",
217 "mediatek,mt2701-infracfg",
258 infracfg = <&infracfg>;
286 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
288 clocks = <&infracfg CLK_INFRA_PMICSPI>,
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Dmt8135.dtsi132 infracfg: infracfg@10001000 { label
135 compatible = "mediatek,mt8135-infracfg", "syscon";
184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
Dmt2701.dtsi131 infracfg: syscon@10001000 { label
132 compatible = "mediatek,mt2701-infracfg", "syscon";
154 infracfg = <&infracfg>;
192 clocks = <&infracfg CLK_INFRA_SMI>,
194 <&infracfg CLK_INFRA_SMI>;
222 clocks = <&infracfg CLK_INFRA_M4U>;
434 clocks = <&infracfg CLK_INFRA_AUDIO>,
/Linux-v4.19/Documentation/devicetree/bindings/rng/
Dmtk-rng.txt18 clocks = <&infracfg CLK_INFRA_TRNG>;
/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dmtk-afe-pcm.txt25 clocks = <&infracfg INFRA_AUDIO>,
Dmt2701-afe-pcm.txt68 clocks = <&infracfg CLK_INFRA_AUDIO>,
/Linux-v4.19/Documentation/devicetree/bindings/media/
Dmtk-cir.txt25 clocks = <&infracfg CLK_INFRA_IRRX>;
/Linux-v4.19/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt40 clocks = <&infracfg CLK_INFRA_GCE>;
/Linux-v4.19/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.txt63 clocks = <&infracfg CLK_INFRA_M4U>;
/Linux-v4.19/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi.txt76 clocks = <&infracfg CLK_INFRA_CEC>;