| /Linux-v4.19/drivers/gpu/drm/i915/ |
| D | intel_uncore.h | 71 i915_reg_t r, bool trace);
73 i915_reg_t r, bool trace);
75 i915_reg_t r, bool trace);
77 i915_reg_t r, bool trace);
80 i915_reg_t r, u8 val, bool trace);
82 i915_reg_t r, u16 val, bool trace);
84 i915_reg_t r, u32 val, bool trace);
119 i915_reg_t reg_set;
120 i915_reg_t reg_ack;
160 i915_reg_t reg, unsigned int op);
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| D | dvo.h | 35 i915_reg_t dvo_reg;
36 i915_reg_t dvo_srcdim_reg;
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| D | intel_uncore.c | 902 static const i915_reg_t gen8_shadowed_regs[] = {
912 static const i915_reg_t gen11_shadowed_regs[] = {
926 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) in mmio_reg_cmp()
941 const i915_reg_t *regs = gen##x##_shadowed_regs; \
1076 const i915_reg_t reg, in __unclaimed_reg_debug()
1090 const i915_reg_t reg, in unclaimed_reg_debug()
1110 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1118 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1184 func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1224 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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| D | intel_dvo.c | 181 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; in intel_disable_dvo()
195 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; in intel_enable_dvo()
272 i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; in intel_dvo_pre_enable()
273 i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; in intel_dvo_pre_enable()
393 static enum port intel_dvo_port(i915_reg_t dvo_reg) in intel_dvo_port()
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| D | intel_drv.h | 1010 i915_reg_t hdmi_reg;
1062 i915_reg_t output_reg;
1146 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1147 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1398 i915_reg_t adpa_reg, enum pipe *pipe);
1671 i915_reg_t dp_reg, enum port port,
1673 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1832 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1850 i915_reg_t lvds_reg, enum pipe *pipe);
2088 i915_reg_t sdvo_reg, enum pipe *pipe);
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| D | intel_dp.c | 812 i915_reg_t pp_ctrl;
813 i915_reg_t pp_stat;
814 i915_reg_t pp_on;
815 i915_reg_t pp_off;
816 i915_reg_t pp_div;
841 static i915_reg_t
851 static i915_reg_t
877 i915_reg_t pp_ctrl_reg, pp_div_reg; in edp_notify_handler()
942 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); in intel_dp_aux_wait_done()
1068 i915_reg_t ch_ctl, ch_data[5]; in intel_dp_aux_xfer()
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| D | intel_hdmi.c | 130 static i915_reg_t
215 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_write_infoframe()
252 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); in ibx_infoframe_enabled()
275 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_write_infoframe()
333 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_write_infoframe()
392 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in hsw_write_infoframe()
550 i915_reg_t reg = VIDEO_DIP_CTL; in g4x_set_infoframes()
666 i915_reg_t reg; in intel_hdmi_set_gcp_infoframe()
701 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_set_infoframes()
753 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_set_infoframes()
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| D | intel_audio.c | 211 i915_reg_t reg_eldv, u32 bits_eldv, in intel_eld_uptodate()
212 i915_reg_t reg_elda, u32 bits_elda, in intel_eld_uptodate()
213 i915_reg_t reg_edid) in intel_eld_uptodate()
491 i915_reg_t aud_config, aud_cntrl_st2; in ilk_audio_codec_disable()
540 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; in ilk_audio_codec_enable()
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| D | i915_gem_fence_reg.c | 63 i915_reg_t fence_reg_lo, fence_reg_hi; in i965_write_fence_reg()
149 i915_reg_t reg = FENCE_REG(fence->id); in i915_write_fence_reg()
181 i915_reg_t reg = FENCE_REG(fence->id); in i830_write_fence_reg()
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| D | intel_fifo_underrun.c | 90 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
111 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
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| D | intel_crt.c | 53 i915_reg_t adpa_reg;
67 i915_reg_t adpa_reg, enum pipe *pipe) in intel_crt_port_enabled()
639 i915_reg_t bclrpat_reg, vtotal_reg, in intel_crt_load_detect()
933 i915_reg_t adpa_reg; in intel_crt_init()
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| D | vlv_dsi.c | 89 i915_reg_t reg, in write_data()
105 i915_reg_t reg, in read_data()
128 i915_reg_t data_reg, ctrl_reg; in intel_dsi_host_transfer()
636 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in vlv_dsi_clear_device_ready()
700 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in intel_dsi_port_enable()
733 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? in intel_dsi_port_disable()
1042 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? in intel_dsi_get_hw_state()
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| D | intel_workarounds.c | 52 i915_reg_t reg, const u32 mask, const u32 val) in wa_add()
937 i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
942 static void whitelist_reg(struct whitelist *w, i915_reg_t reg) in whitelist_reg()
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| D | intel_wopcm.c | 214 i915_reg_t reg, u32 val, u32 mask, in write_and_verify()
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| D | intel_lvds.c | 67 i915_reg_t reg;
87 i915_reg_t lvds_reg, enum pipe *pipe) in intel_lvds_port_enabled()
869 i915_reg_t lvds_reg; in intel_lvds_init()
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| D | intel_psr.c | 641 i915_reg_t psr_status; in intel_psr_disable_source()
724 i915_reg_t reg; in intel_psr_wait_for_idle()
760 i915_reg_t reg; in __psr_wait_for_idle_locked()
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| D | intel_ringbuffer.c | 358 i915_reg_t mmio; in intel_ring_setup_status_page()
408 i915_reg_t reg = RING_INSTPM(engine->mmio_base); in intel_ring_setup_status_page()
676 i915_reg_t mbox_reg; in gen6_signal()
1611 i915_reg_t last_reg = {}; /* keep gcc quiet */ in mi_set_context()
2082 i915_reg_t mbox_reg; in intel_ring_init_semaphores()
2106 i915_reg_t mbox_reg; in intel_ring_init_semaphores()
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| D | i915_drv.h | 471 i915_reg_t mmioaddr[8];
662 i915_reg_t gpio_reg;
1324 i915_reg_t addr;
3525 const i915_reg_t reg);
3530 const i915_reg_t reg) in intel_rc6_residency_us()
3579 i915_reg_t reg) \
3586 i915_reg_t reg, uint##x##_t val) \
3639 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) in i915_vgacntrl_reg()
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| D | i915_irq.c | 169 i915_reg_t reg) in gen3_assert_iir_is_zero()
185 i915_reg_t reg) in gen2_assert_iir_is_zero()
360 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) in gen6_pm_iir()
367 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) in gen6_pm_imr()
377 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) in gen6_pm_ier()
437 i915_reg_t reg = gen6_pm_iir(dev_priv); in gen6_reset_pm_iir()
707 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
730 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
825 i915_reg_t high_frame, low_frame; in i915_get_vblank_counter()
1397 i915_reg_t reg; in ivybridge_parity_work()
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| D | intel_mocs.c | 208 static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index) in mocs_register()
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| /Linux-v4.19/drivers/gpu/drm/i915/selftests/ |
| D | intel_uncore.c | 65 const i915_reg_t *regs; in intel_shadow_table_check()
71 const i915_reg_t *reg; in intel_shadow_table_check()
149 i915_reg_t reg = { offset }; in intel_uncore_check_forcewake_domains()
160 i915_reg_t reg = { offset }; in intel_uncore_check_forcewake_domains()
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| D | mock_uncore.c | 29 nop_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { return 0; }
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| /Linux-v4.19/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.h | 41 i915_reg_t reg;
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| D | mmio_context.c | 163 i915_reg_t offset; in load_render_mocs()
343 i915_reg_t reg; in handle_tlb_pending_event()
389 i915_reg_t offset, l3_offset; in switch_mocs()
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| D | interrupt.h | 175 i915_reg_t reg_base;
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