812 	i915_reg_t pp_ctrl;
813 	i915_reg_t pp_stat;
814 	i915_reg_t pp_on;
815 	i915_reg_t pp_off;
816 	i915_reg_t pp_div;
841 static i915_reg_t
851 static i915_reg_t
877 		i915_reg_t pp_ctrl_reg, pp_div_reg;  in edp_notify_handler()
942 	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);  in intel_dp_aux_wait_done()
1068 	i915_reg_t ch_ctl, ch_data[5];  in intel_dp_aux_xfer()
1382 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)  in g4x_aux_ctl_reg()
1398 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)  in g4x_aux_data_reg()
1414 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)  in ilk_aux_ctl_reg()
1432 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)  in ilk_aux_data_reg()
1450 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)  in skl_aux_ctl_reg()
1469 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)  in skl_aux_data_reg()
2034 	i915_reg_t pp_stat_reg, pp_ctrl_reg;  in wait_panel_status()
2133 	i915_reg_t pp_stat_reg, pp_ctrl_reg;  in edp_panel_vdd_on()
2205 	i915_reg_t pp_stat_reg, pp_ctrl_reg;  in edp_panel_vdd_off_sync()
2289 	i915_reg_t pp_ctrl_reg;  in edp_panel_on()
2347 	i915_reg_t pp_ctrl_reg;  in edp_panel_off()
2395 	i915_reg_t pp_ctrl_reg;  in _intel_edp_backlight_on()
2438 	i915_reg_t pp_ctrl_reg;  in _intel_edp_backlight_off()
2659 			   i915_reg_t dp_reg, enum port port,  in intel_dp_port_enabled()
3050 	i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);  in vlv_detach_power_sequencer()
5725 		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);  in intel_dp_set_drrs_state()
6289 		   i915_reg_t output_reg,  in intel_dp_init()