| /Linux-v4.19/drivers/gpu/drm/i915/gvt/ |
| D | opregion.c | 269 gvt_vgpu_err("fail to get MFN from VA\n"); in map_vgpu_opregion()
276 gvt_vgpu_err("fail to map GFN to MFN, errno: %d\n", in map_vgpu_opregion()
323 gvt_vgpu_err("not supported hypervisor\n"); in intel_vgpu_opregion_base_write_handler()
491 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
499 gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
506 gvt_vgpu_err("not supported hypervisor\n"); in intel_vgpu_emulate_opregion_request()
511 gvt_vgpu_err("requesting SMI service\n"); in intel_vgpu_emulate_opregion_request()
524 gvt_vgpu_err("requesting runtime service: func \"%s\"," in intel_vgpu_emulate_opregion_request()
551 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
559 gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", in intel_vgpu_emulate_opregion_request()
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| D | dmabuf.c | 242 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); in vgpu_get_plane_info()
272 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
277 gvt_vgpu_err("fb size is zero\n"); in vgpu_get_plane_info()
282 gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); in vgpu_get_plane_info()
287 gvt_vgpu_err("Invalid GTT offset or size\n"); in vgpu_get_plane_info()
292 gvt_vgpu_err("invalid gma addr\n"); in vgpu_get_plane_info()
416 gvt_vgpu_err("alloc dmabuf_obj failed\n"); in intel_vgpu_query_plane()
424 gvt_vgpu_err("allocate intel vgpu fb info failed\n"); in intel_vgpu_query_plane()
446 gvt_vgpu_err("get vfio device failed\n"); in intel_vgpu_query_plane()
487 gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id); in intel_vgpu_get_dmabuf()
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| D | fb_decoder.c | 231 gvt_vgpu_err("Out-of-bounds pixel format index\n"); in intel_vgpu_decode_primary_plane()
245 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); in intel_vgpu_decode_primary_plane()
257 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_primary_plane()
359 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); in intel_vgpu_decode_cursor_plane()
382 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_cursor_plane()
441 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); in intel_vgpu_decode_sprite_plane()
486 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", in intel_vgpu_decode_sprite_plane()
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| D | execlist.c | 203 gvt_vgpu_err("schedule out context is not running context," in emulate_execlist_ctx_schedule_out()
274 gvt_vgpu_err("virtual execlist slots are full\n"); in get_next_execlist_slot()
295 gvt_vgpu_err("no available execlist slot\n"); in emulate_execlist_schedule_in()
394 gvt_vgpu_err("fail to emulate execlist schedule in\n"); in prepare_execlist_workload()
476 gvt_vgpu_err("invalid elsp submission, desc0 is invalid\n"); in intel_vgpu_submit_execlist()
484 gvt_vgpu_err("unexpected GGTT elsp submission\n"); in intel_vgpu_submit_execlist()
495 gvt_vgpu_err("failed to submit desc %d\n", i); in intel_vgpu_submit_execlist()
503 gvt_vgpu_err("descriptors content: desc0 %08x %08x desc1 %08x %08x\n", in intel_vgpu_submit_execlist()
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| D | cmd_parser.c | 869 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", in cmd_reg_handler()
875 gvt_vgpu_err("%s access to non-render register (%x)\n", in cmd_reg_handler()
881 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset); in cmd_reg_handler()
1258 gvt_vgpu_err("unknown plane code %d\n", plane); in skl_decode_mi_display_flip()
1370 gvt_vgpu_err("fail to decode MI display flip command\n"); in cmd_handler_mi_display_flip()
1376 gvt_vgpu_err("invalid MI display flip command\n"); in cmd_handler_mi_display_flip()
1382 gvt_vgpu_err("fail to update plane mmio\n"); in cmd_handler_mi_display_flip()
1420 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); in get_gma_bb_from_cmd()
1443 gvt_vgpu_err("command address audit fail name %s\n", in cmd_address_audit()
1461 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", in cmd_address_audit()
[all …]
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| D | edid.c | 55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n"); in edid_get_byte()
59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n"); in edid_get_byte()
64 gvt_vgpu_err("Reading EDID but EDID is not available!\n"); in edid_get_byte()
75 gvt_vgpu_err("No EDID available during the reading?\n"); in edid_get_byte()
244 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); in gmbus1_mmio_write()
313 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n"); in gmbus3_mmio_read()
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| D | scheduler.c | 152 gvt_vgpu_err("Invalid guest context descriptor\n"); in populate_shadow_context()
307 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", in copy_workload_to_ring_buffer()
368 gvt_vgpu_err("fail to pin shadow context\n"); in intel_gvt_scan_and_shadow_workload()
392 gvt_vgpu_err("fail to allocate gem request\n"); in intel_gvt_scan_and_shadow_workload()
579 gvt_vgpu_err("fail to vgpu pin mm\n"); in prepare_workload()
587 gvt_vgpu_err("fail to vgpu sync oos pages\n"); in prepare_workload()
593 gvt_vgpu_err("fail to flush post shadow\n"); in prepare_workload()
599 gvt_vgpu_err("fail to generate request\n"); in prepare_workload()
605 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n"); in prepare_workload()
611 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n"); in prepare_workload()
[all …]
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| D | gtt.c | 58 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n", in intel_gvt_ggtt_validate_range()
821 gvt_vgpu_err("fail to allocate ppgtt shadow page\n"); in ppgtt_alloc_spt()
836 gvt_vgpu_err("fail to map dma addr\n"); in ppgtt_alloc_spt()
946 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n", in ppgtt_invalidate_spt_by_shadow_entry()
1019 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n", in ppgtt_invalidate_spt()
1095 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt_by_guest_entry()
1250 gvt_vgpu_err("GVT doesn't support 1GB entry\n"); in ppgtt_populate_shadow_entry()
1305 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_populate_spt()
1334 gvt_vgpu_err("fail to find guest page\n"); in ppgtt_handle_guest_entry_removal()
1350 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", in ppgtt_handle_guest_entry_removal()
[all …]
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| D | kvmgt.c | 151 gvt_vgpu_err("vfio_pin_pages failed for gfn 0x%lx, ret %d\n", in gvt_pin_guest_page()
157 gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn); in gvt_pin_guest_page()
166 gvt_vgpu_err("The pages are not continuous\n"); in gvt_pin_guest_page()
194 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", in gvt_dma_map_page()
411 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); in intel_vgpu_reg_rw_opregion()
461 gvt_vgpu_err("failed to get vfio device\n"); in kvmgt_get_vfio_device()
517 gvt_vgpu_err("failed to find type %s to create\n", in intel_vgpu_create()
616 gvt_vgpu_err("vfio_register_notifier for iommu failed: %d\n", in intel_vgpu_open()
625 gvt_vgpu_err("vfio_register_notifier for group failed: %d\n", in intel_vgpu_open()
761 gvt_vgpu_err("Invalid aperture offset %llu\n", off); in intel_vgpu_aperture_rw()
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| D | debug.h | 30 #define gvt_vgpu_err(fmt, args...) \ macro
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| D | mmio.c | 156 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", in intel_vgpu_emulate_mmio_read()
220 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, in intel_vgpu_emulate_mmio_write()
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| D | aperture_gm.c | 210 gvt_vgpu_err("Failed to alloc fences\n"); in alloc_vgpu_fence()
241 gvt_vgpu_err("Invalid vGPU creation params\n"); in alloc_resource()
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| D | handlers.c | 196 gvt_vgpu_err("access oob fence reg %d/%d\n", in sanitize_fence_mmio_access()
228 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", in gamw_echo_dev_rw_ia_write()
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
596 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); in check_fdi_rx_train_status()
654 gvt_vgpu_err("Unsupport registers %x\n", offset); in update_fdi_rx_iir_status()
884 gvt_vgpu_err("Unsupported DP port access!\n"); in dp_aux_ch_ctl_mmio_write()
944 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1011 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1097 gvt_vgpu_err("SBI caching meets maximum limits\n"); in write_virtual_sbi_register()
1177 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", in pvinfo_mmio_read()
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| D | mmio_context.c | 376 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id); in handle_tlb_pending_event()
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