Lines Matching refs:gvt_vgpu_err
196 gvt_vgpu_err("access oob fence reg %d/%d\n", in sanitize_fence_mmio_access()
228 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", in gamw_echo_dev_rw_ia_write()
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
596 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); in check_fdi_rx_train_status()
654 gvt_vgpu_err("Unsupport registers %x\n", offset); in update_fdi_rx_iir_status()
884 gvt_vgpu_err("Unsupported DP port access!\n"); in dp_aux_ch_ctl_mmio_write()
944 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1011 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); in dp_aux_ch_ctl_mmio_write()
1097 gvt_vgpu_err("SBI caching meets maximum limits\n"); in write_virtual_sbi_register()
1177 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", in pvinfo_mmio_read()
1206 gvt_vgpu_err("Invalid PV notification %d\n", notification); in handle_g2v_notification()
1262 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", in pvinfo_mmio_write()
1459 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", in hws_pga_write()
1469 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", in hws_pga_write()
1664 gvt_vgpu_err("fail submit workload on ring %d\n", in elsp_mmio_write()
3510 gvt_vgpu_err("try to write RO reg %x\n", offset); in intel_vgpu_mmio_reg_rw()