Home
last modified time | relevance | path

Searched refs:ext_misc_reg (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/clk/tegra/
Dclk-tegra210.c675 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); in _pll_misc_chk_default()
729 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
731 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
733 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
735 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
793 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
796 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
806 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
808 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
846 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
[all …]
Dclk-tegra124.c277 .ext_misc_reg[0] = 0x4f0,
278 .ext_misc_reg[1] = 0x4f4,
279 .ext_misc_reg[2] = 0x4f8,
299 .ext_misc_reg[0] = 0x504,
300 .ext_misc_reg[1] = 0x508,
301 .ext_misc_reg[2] = 0x50c,
359 .ext_misc_reg[0] = 0x5ac,
360 .ext_misc_reg[1] = 0x5b0,
361 .ext_misc_reg[2] = 0x5b4,
657 .ext_misc_reg[0] = 0x570,
[all …]
Dclk-tegra114.c254 .ext_misc_reg[0] = 0x4f0,
255 .ext_misc_reg[1] = 0x4f4,
256 .ext_misc_reg[2] = 0x4f8,
276 .ext_misc_reg[0] = 0x504,
277 .ext_misc_reg[1] = 0x508,
278 .ext_misc_reg[2] = 0x50c,
Dclk-pll.c2186 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2187 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2188 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2323 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2324 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2325 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
Dclk.h273 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; member