Lines Matching refs:ext_misc_reg
675 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); in _pll_misc_chk_default()
729 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
731 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
733 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
735 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
793 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
796 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
806 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
808 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
846 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
855 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
859 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
861 plld->params->ext_misc_reg[1]); in tegra210_plld_set_defaults()
909 } else if (plldss->params->ext_misc_reg[1]) { in plldss_defaults()
927 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
930 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
942 if (!plldss->params->ext_misc_reg[1]) { in plldss_defaults()
944 plldss->params->ext_misc_reg[0]); in plldss_defaults()
950 plldss->params->ext_misc_reg[0]); in plldss_defaults()
953 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
954 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
955 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
1019 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1022 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1033 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1127 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1130 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1133 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1141 pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1145 pllx->params->ext_misc_reg[1]); in tegra210_pllx_set_defaults()
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1152 pllx->params->ext_misc_reg[3]); in tegra210_pllx_set_defaults()
1156 pllx->params->ext_misc_reg[4]); in tegra210_pllx_set_defaults()
1158 pllx->params->ext_misc_reg[5]); in tegra210_pllx_set_defaults()
1183 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1186 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1194 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1241 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1245 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1253 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1256 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1260 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1304 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1307 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1309 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1312 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1320 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1322 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1366 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1369 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1372 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1374 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1377 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], in tegra210_pllx_dyn_ramp()
1387 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1593 .ext_misc_reg[0] = PLLX_MISC0,
1594 .ext_misc_reg[1] = PLLX_MISC1,
1595 .ext_misc_reg[2] = PLLX_MISC2,
1596 .ext_misc_reg[3] = PLLX_MISC3,
1597 .ext_misc_reg[4] = PLLX_MISC4,
1598 .ext_misc_reg[5] = PLLX_MISC5,
1648 .ext_misc_reg[0] = PLLC_MISC0,
1649 .ext_misc_reg[1] = PLLC_MISC1,
1650 .ext_misc_reg[2] = PLLC_MISC2,
1651 .ext_misc_reg[3] = PLLC_MISC3,
1691 .ext_misc_reg[0] = PLLC2_MISC0,
1692 .ext_misc_reg[1] = PLLC2_MISC1,
1693 .ext_misc_reg[2] = PLLC2_MISC2,
1694 .ext_misc_reg[3] = PLLC2_MISC3,
1721 .ext_misc_reg[0] = PLLC3_MISC0,
1722 .ext_misc_reg[1] = PLLC3_MISC1,
1723 .ext_misc_reg[2] = PLLC3_MISC2,
1724 .ext_misc_reg[3] = PLLC3_MISC3,
1778 .ext_misc_reg[0] = PLLC4_MISC0,
1835 .ext_misc_reg[0] = PLLM_MISC2,
1836 .ext_misc_reg[1] = PLLM_MISC1,
1861 .ext_misc_reg[0] = PLLMB_MISC1,
1941 .ext_misc_reg[0] = PLLRE_MISC0,
1981 .ext_misc_reg[0] = PLLP_MISC0,
1982 .ext_misc_reg[1] = PLLP_MISC1,
2009 .ext_misc_reg[0] = PLLA1_MISC0,
2010 .ext_misc_reg[1] = PLLA1_MISC1,
2011 .ext_misc_reg[2] = PLLA1_MISC2,
2012 .ext_misc_reg[3] = PLLA1_MISC3,
2061 .ext_misc_reg[0] = PLLA_MISC0,
2062 .ext_misc_reg[1] = PLLA_MISC1,
2063 .ext_misc_reg[2] = PLLA_MISC2,
2108 .ext_misc_reg[0] = PLLD_MISC0,
2109 .ext_misc_reg[1] = PLLD_MISC1,
2150 .ext_misc_reg[0] = PLLD2_MISC0,
2151 .ext_misc_reg[1] = PLLD2_MISC1,
2152 .ext_misc_reg[2] = PLLD2_MISC2,
2153 .ext_misc_reg[3] = PLLD2_MISC3,
2193 .ext_misc_reg[0] = PLLDP_MISC,
2194 .ext_misc_reg[1] = PLLDP_SS_CFG,
2195 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2196 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2236 .ext_misc_reg[0] = PLLU_MISC0,
2237 .ext_misc_reg[1] = PLLU_MISC1,
2846 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2848 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()