| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 508 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
518 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
525 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
526 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
545 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
548 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
551 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
553 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
558 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
559 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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| D | vega10_hwmgr.c | 1196 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1201 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1204 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1206 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1208 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1209 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1216 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1267 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1309 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1311 dpm_table, in vega10_setup_default_dpm_tables()
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| D | smu7_hwmgr.c | 552 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
563 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
569 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
573 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
604 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
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| D | smu_helper.c | 303 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
305 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
307 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
308 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
318 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
319 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
320 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
321 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
328 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
330 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
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| D | smu7_hwmgr.h | 203 struct smu7_dpm_table dpm_table; member
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| D | vega10_hwmgr.h | 310 struct vega10_dpm_table dpm_table; member
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| D | vega12_hwmgr.h | 314 struct vega12_dpm_table dpm_table; member
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | fiji_smumgr.c | 502 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
514 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
516 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
524 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
526 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
529 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
531 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
533 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
535 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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| D | iceland_smumgr.c | 767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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| D | ci_smumgr.c | 473 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
483 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
485 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
491 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
498 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
500 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
717 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
723 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
724 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
726 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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| D | vegam_smumgr.c | 574 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
591 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
866 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
870 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
886 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
889 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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| D | tonga_smumgr.c | 500 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
505 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
507 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
509 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
521 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
523 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
681 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
683 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
700 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
702 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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| D | polaris10_smumgr.c | 770 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
775 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
777 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
779 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
787 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
791 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
980 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
984 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1000 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1003 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 433 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
441 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
442 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
445 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
447 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
449 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
452 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
453 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
455 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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| D | ci_dpm.h | 194 struct ci_dpm_table dpm_table; member
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 558 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
566 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
567 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
569 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
570 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
572 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
574 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
577 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
578 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
580 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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| D | ci_dpm.h | 195 struct ci_dpm_table dpm_table; member
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