558 	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;  in ci_populate_bapm_parameters_in_dpm_table()  local
566 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
567 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
569 	dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;  in ci_populate_bapm_parameters_in_dpm_table()
570 	dpm_table->GpuTjMax =  in ci_populate_bapm_parameters_in_dpm_table()
572 	dpm_table->GpuTjHyst = 8;  in ci_populate_bapm_parameters_in_dpm_table()
574 	dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;  in ci_populate_bapm_parameters_in_dpm_table()
577 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);  in ci_populate_bapm_parameters_in_dpm_table()
578 		dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);  in ci_populate_bapm_parameters_in_dpm_table()
580 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
581 		dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
584 	dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);  in ci_populate_bapm_parameters_in_dpm_table()
591 				dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);  in ci_populate_bapm_parameters_in_dpm_table()
592 				dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);  in ci_populate_bapm_parameters_in_dpm_table()
2691 	for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {  in ci_do_program_memory_timing_parameters()
2692 		for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {  in ci_do_program_memory_timing_parameters()
2694 								   pi->dpm_table.sclk_table.dpm_levels[i].value,  in ci_do_program_memory_timing_parameters()
2695 								   pi->dpm_table.mclk_table.dpm_levels[j].value,  in ci_do_program_memory_timing_parameters()
2746 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)  in ci_get_dpm_level_enable_mask_value()  argument
2751 	for (i = dpm_table->count; i > 0; i--) {  in ci_get_dpm_level_enable_mask_value()
2753 		if (dpm_table->dpm_levels[i-1].enabled)  in ci_get_dpm_level_enable_mask_value()
2766 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_smc_link_level()  local
2769 	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {  in ci_populate_smc_link_level()
2771 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;  in ci_populate_smc_link_level()
2773 			amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);  in ci_populate_smc_link_level()
2779 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;  in ci_populate_smc_link_level()
2781 		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);  in ci_populate_smc_link_level()
3422 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_graphic_levels()  local
3432 	for (i = 0; i < dpm_table->sclk_table.count; i++) {  in ci_populate_all_graphic_levels()
3434 						       dpm_table->sclk_table.dpm_levels[i].value,  in ci_populate_all_graphic_levels()
3441 		if (i == (dpm_table->sclk_table.count - 1))  in ci_populate_all_graphic_levels()
3447 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;  in ci_populate_all_graphic_levels()
3449 		ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);  in ci_populate_all_graphic_levels()
3469 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_memory_levels()  local
3479 	for (i = 0; i < dpm_table->mclk_table.count; i++) {  in ci_populate_all_memory_levels()
3480 		if (dpm_table->mclk_table.dpm_levels[i].value == 0)  in ci_populate_all_memory_levels()
3483 						      dpm_table->mclk_table.dpm_levels[i].value,  in ci_populate_all_memory_levels()
3489 	if ((dpm_table->mclk_table.count >= 2) &&  in ci_populate_all_memory_levels()
3499 	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;  in ci_populate_all_memory_levels()
3501 		ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);  in ci_populate_all_memory_levels()
3503 	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =  in ci_populate_all_memory_levels()
3516 				      struct ci_single_dpm_table* dpm_table,  in ci_reset_single_dpm_table()  argument
3521 	dpm_table->count = count;  in ci_reset_single_dpm_table()
3523 		dpm_table->dpm_levels[i].enabled = false;  in ci_reset_single_dpm_table()
3526 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,  in ci_setup_pcie_table_entry()  argument
3529 	dpm_table->dpm_levels[index].value = pcie_gen;  in ci_setup_pcie_table_entry()
3530 	dpm_table->dpm_levels[index].param1 = pcie_lanes;  in ci_setup_pcie_table_entry()
3531 	dpm_table->dpm_levels[index].enabled = true;  in ci_setup_pcie_table_entry()
3550 				  &pi->dpm_table.pcie_speed_table,  in ci_setup_default_pcie_tables()
3554 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3558 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3561 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,  in ci_setup_default_pcie_tables()
3564 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,  in ci_setup_default_pcie_tables()
3567 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,  in ci_setup_default_pcie_tables()
3570 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,  in ci_setup_default_pcie_tables()
3573 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,  in ci_setup_default_pcie_tables()
3577 	pi->dpm_table.pcie_speed_table.count = 6;  in ci_setup_default_pcie_tables()
3602 	memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));  in ci_setup_default_dpm_tables()
3605 				  &pi->dpm_table.sclk_table,  in ci_setup_default_dpm_tables()
3608 				  &pi->dpm_table.mclk_table,  in ci_setup_default_dpm_tables()
3611 				  &pi->dpm_table.vddc_table,  in ci_setup_default_dpm_tables()
3614 				  &pi->dpm_table.vddci_table,  in ci_setup_default_dpm_tables()
3617 				  &pi->dpm_table.mvdd_table,  in ci_setup_default_dpm_tables()
3620 	pi->dpm_table.sclk_table.count = 0;  in ci_setup_default_dpm_tables()
3623 		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3625 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =  in ci_setup_default_dpm_tables()
3627 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3629 			pi->dpm_table.sclk_table.count++;  in ci_setup_default_dpm_tables()
3633 	pi->dpm_table.mclk_table.count = 0;  in ci_setup_default_dpm_tables()
3636 		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3638 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =  in ci_setup_default_dpm_tables()
3640 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3642 			pi->dpm_table.mclk_table.count++;  in ci_setup_default_dpm_tables()
3647 		pi->dpm_table.vddc_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3649 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =  in ci_setup_default_dpm_tables()
3651 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3653 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;  in ci_setup_default_dpm_tables()
3658 			pi->dpm_table.vddci_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3660 			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3662 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3668 			pi->dpm_table.mvdd_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3670 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3672 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3678 	memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),  in ci_setup_default_dpm_tables()
3774 	ret = ci_find_boot_level(&pi->dpm_table.sclk_table,  in ci_init_smc_table()
3778 	ret = ci_find_boot_level(&pi->dpm_table.mclk_table,  in ci_init_smc_table()
3811 	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;  in ci_init_smc_table()
3849 				      struct ci_single_dpm_table *dpm_table,  in ci_trim_single_dpm_states()  argument
3854 	for (i = 0; i < dpm_table->count; i++) {  in ci_trim_single_dpm_states()
3855 		if ((dpm_table->dpm_levels[i].value < low_limit) ||  in ci_trim_single_dpm_states()
3856 		    (dpm_table->dpm_levels[i].value > high_limit))  in ci_trim_single_dpm_states()
3857 			dpm_table->dpm_levels[i].enabled = false;  in ci_trim_single_dpm_states()
3859 			dpm_table->dpm_levels[i].enabled = true;  in ci_trim_single_dpm_states()
3868 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;  in ci_trim_pcie_dpm_states()
3910 				  &pi->dpm_table.sclk_table,  in ci_trim_dpm_states()
3915 				  &pi->dpm_table.mclk_table,  in ci_trim_dpm_states()
4007 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
4009 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
4048 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
4055 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4058 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4326 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);  in ci_generate_dpm_level_enable_mask()
4328 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);  in ci_generate_dpm_level_enable_mask()
4336 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);  in ci_generate_dpm_level_enable_mask()
4893 	for (i = 0; i < pi->dpm_table.mclk_table.count; i++)  in ci_convert_mc_reg_table_to_smc()
4895 						     pi->dpm_table.mclk_table.dpm_levels[i].value,  in ci_convert_mc_reg_table_to_smc()
4934 				    pi->dpm_table.mclk_table.count,  in ci_update_and_upload_mc_reg_table()
5836 	SMU7_Discrete_DpmTable *dpm_table;  in ci_dpm_init()  local
5968 	dpm_table = &pi->smc_state_table;  in ci_dpm_init()
5972 		dpm_table->VRHotGpio = gpio.shift;  in ci_dpm_init()
5975 		dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()
5981 		dpm_table->AcDcGpio = gpio.shift;  in ci_dpm_init()
5984 		dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()
6543 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;  in ci_dpm_print_clock_levels()
6544 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;  in ci_dpm_print_clock_levels()
6545 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;  in ci_dpm_print_clock_levels()
6658 	struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);  in ci_dpm_get_sclk_od()
6694 	struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);  in ci_dpm_get_mclk_od()