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/Linux-v4.19/drivers/clk/tegra/
Dclk-divider.c32 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
37 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
38 divider->frac_width, divider->flags); in get_div()
49 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
54 reg = readl_relaxed(divider->reg) >> divider->shift; in clk_frac_div_recalc_rate()
55 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
57 mul = get_mul(divider); in clk_frac_div_recalc_rate()
70 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
77 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
81 mul = get_mul(divider); in clk_frac_div_round_rate()
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/Linux-v4.19/drivers/clk/qcom/
Dclk-regmap-divider.c29 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
30 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
33 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
34 val >>= divider->shift; in div_round_ro_rate()
35 val &= BIT(divider->width) - 1; in div_round_ro_rate()
37 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
44 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
46 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
53 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
54 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
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/Linux-v4.19/drivers/clk/mvebu/
Ddove-divider.c53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
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/Linux-v4.19/drivers/clk/ti/
Ddivider.c42 static unsigned int _get_maxdiv(struct clk_omap_divider *divider) in _get_maxdiv() argument
44 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
45 return div_mask(divider); in _get_maxdiv()
46 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_maxdiv()
47 return 1 << div_mask(divider); in _get_maxdiv()
48 if (divider->table) in _get_maxdiv()
49 return _get_table_maxdiv(divider->table); in _get_maxdiv()
50 return div_mask(divider) + 1; in _get_maxdiv()
64 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
66 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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Dclk-dra7-atl.c57 u32 divider; /* Cached divider value */ member
93 cdesc->divider - 1); in atl_clk_enable()
128 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
134 unsigned divider; in atl_clk_round_rate() local
136 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
138 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
140 return *parent_rate / divider; in atl_clk_round_rate()
147 u32 divider; in atl_clk_set_rate() local
153 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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/Linux-v4.19/drivers/clk/rockchip/
Dclk-half-divider.c24 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
27 val = clk_readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
28 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
97 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
101 divider->width, in clk_half_divider_round_rate()
102 divider->flags); in clk_half_divider_round_rate()
110 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
117 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
119 if (divider->lock) in clk_half_divider_set_rate()
120 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
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/Linux-v4.19/drivers/clk/mxs/
Dclk-div.c28 struct clk_divider divider; member
36 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
38 return container_of(divider, struct clk_div, divider); in to_clk_div()
46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
54 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
96 div->divider.reg = reg; in mxs_clk_div()
97 div->divider.shift = shift; in mxs_clk_div()
98 div->divider.width = width; in mxs_clk_div()
99 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
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/Linux-v4.19/drivers/clk/imx/
Dclk-fixup-div.c30 struct clk_divider divider; member
37 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
39 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
47 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
55 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
63 unsigned int divider, value; in clk_fixup_div_set_rate() local
67 divider = parent_rate / rate; in clk_fixup_div_set_rate()
70 value = divider - 1; in clk_fixup_div_set_rate()
115 fixup_div->divider.reg = reg; in imx_clk_fixup_divider()
116 fixup_div->divider.shift = shift; in imx_clk_fixup_divider()
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/Linux-v4.19/drivers/clk/
Dclk-divider.c138 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
141 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
142 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
144 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate()
145 divider->flags, divider->width); in clk_divider_recalc_rate()
370 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_round_rate() local
373 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_round_rate()
376 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_round_rate()
377 val &= clk_div_mask(divider->width); in clk_divider_round_rate()
379 return divider_ro_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
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Dclk-cdce925.c380 unsigned long divider; in cdce925_calc_divider() local
387 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_calc_divider()
388 if (divider > 0x7F) in cdce925_calc_divider()
389 divider = 0x7F; in cdce925_calc_divider()
391 return (u16)divider; in cdce925_calc_divider()
441 u16 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() local
443 if (l_parent_rate / divider != rate) { in cdce925_clk_round_rate()
445 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate()
449 if (divider) in cdce925_clk_round_rate()
450 return (long)(l_parent_rate / divider); in cdce925_clk_round_rate()
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/Linux-v4.19/Documentation/devicetree/bindings/iio/afe/
Dvoltage-divider.txt1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
79 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
85 compatible = "ti,divider-clock";
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/Linux-v4.19/drivers/clk/davinci/
Dpll.c244 struct clk_divider *divider; in davinci_pll_div_register() local
255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
262 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
263 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
266 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
271 NULL, NULL, &divider->hw, divider_ops, in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
579 struct clk_divider *divider; in davinci_pll_obsclk_register() local
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/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/Linux-v4.19/drivers/media/i2c/cx25840/
Dcx25840-ir.c154 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
157 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
167 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
169 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
179 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
183 (divider + 1) * rollovers); in clock_divider_to_freq()
224 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
231 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
235 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
244 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
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/Linux-v4.19/drivers/media/pci/cx23885/
Dcx23888-ir.c193 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
196 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
206 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
208 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
218 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
222 (divider + 1) * rollovers); in clock_divider_to_freq()
263 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
270 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
274 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
283 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
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/Linux-v4.19/arch/arm/boot/dts/
Ddra7xx-clocks.dtsi214 compatible = "ti,divider-clock";
225 compatible = "ti,divider-clock";
234 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
277 compatible = "ti,divider-clock";
303 compatible = "ti,divider-clock";
347 compatible = "ti,divider-clock";
385 compatible = "ti,divider-clock";
423 compatible = "ti,divider-clock";
436 compatible = "ti,divider-clock";
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Domap54xx-clocks.dtsi120 compatible = "ti,divider-clock";
137 compatible = "ti,divider-clock";
146 compatible = "ti,divider-clock";
163 compatible = "ti,divider-clock";
193 compatible = "ti,divider-clock";
218 compatible = "ti,divider-clock";
227 compatible = "ti,divider-clock";
236 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
254 compatible = "ti,divider-clock";
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Domap44xx-clocks.dtsi151 compatible = "ti,divider-clock";
170 compatible = "ti,divider-clock";
180 compatible = "ti,divider-clock";
212 compatible = "ti,divider-clock";
223 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
253 compatible = "ti,divider-clock";
261 compatible = "ti,divider-clock";
270 compatible = "ti,divider-clock";
279 compatible = "ti,divider-clock";
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Ddm816x-clocks.dtsi99 compatible = "ti,divider-clock";
117 compatible = "ti,divider-clock";
125 compatible = "ti,divider-clock";
133 compatible = "ti,divider-clock";
141 compatible = "ti,divider-clock";
149 compatible = "ti,divider-clock";
157 compatible = "ti,divider-clock";
165 compatible = "ti,divider-clock";
173 compatible = "ti,divider-clock";
189 compatible = "ti,divider-clock";
/Linux-v4.19/Documentation/devicetree/bindings/regulator/
Dltc3676.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <127000 200000>;
48 lltc,fb-voltage-divider = <301000 200000>;
57 lltc,fb-voltage-divider = <127000 200000>;
66 lltc,fb-voltage-divider = <221000 200000>;
75 lltc,fb-voltage-divider = <487000 200000>;
89 lltc,fb-voltage-divider = <634000 200000>;
Dltc3589.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <100000 158000>;
48 lltc,fb-voltage-divider = <180000 191000>;
57 lltc,fb-voltage-divider = <270000 100000>;
66 lltc,fb-voltage-divider = <511000 158000>;
74 lltc,fb-voltage-divider = <100000 158000>;
82 lltc,fb-voltage-divider = <180000 191000>;
/Linux-v4.19/drivers/cpufreq/
Darmada-37xx-cpufreq.c94 u8 divider[LOAD_LEVEL_NR]; member
99 {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
100 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
101 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
102 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
123 struct clk *clk, u8 *divider) in armada37xx_cpufreq_dvfs_setup() argument
149 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF; in armada37xx_cpufreq_dvfs_setup()
278 freq = dvfs->cpu_freq_max / dvfs->divider[load_level]; in armada37xx_cpufreq_avs_setup()
428 armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider); in armada37xx_cpufreq_driver_init()
434 freq = cur_frequency / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_init()
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