Searched refs:current_sclk (Results 1 – 23 of 23) sorted by relevance
201 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()218 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()222 rdev->pm.current_sclk = sclk; in radeon_set_power_state()1238 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume_old()1306 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()1372 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()1880 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); in radeon_debugfs_pm_info()
1404 u32 current_sclk; in trinity_patch_thermal_state() local1409 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()1412 current_sclk = pi->boot_pl.sclk; in trinity_patch_thermal_state()1417 if (ps->levels[0].sclk > current_sclk) in trinity_patch_thermal_state()1418 ps->levels[0].sclk = current_sclk; in trinity_patch_thermal_state()
1050 u32 current_sclk; in sumo_patch_thermal_state() local1055 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()1058 current_sclk = pi->boot_pl.sclk; in sumo_patch_thermal_state()1063 if (ps->levels[0].sclk > current_sclk) in sumo_patch_thermal_state()1064 ps->levels[0].sclk = current_sclk; in sumo_patch_thermal_state()
341 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_get_clock_info()
586 *value = rdev->pm.current_sclk / 100; in radeon_info_ioctl()
238 u32 sclk = rdev->pm.current_sclk; in radeon_get_i2c_prescale()
292 selected_sclk = rdev->pm.current_sclk; in rs690_crtc_bandwidth_compute()
719 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info()
973 selected_sclk = rdev->pm.current_sclk; in rv515_crtc_bandwidth_compute()
2183 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()2210 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2332 wm_high.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()2359 wm_low.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
1620 u32 current_sclk; member
9273 wm_high.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()9313 wm_low.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()
267 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atomfirmware_get_clock_info()
411 u32 current_sclk; member
973 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()1012 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
844 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()871 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
1064 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()1103 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1038 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()1077 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
717 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atombios_get_clock_info()
3014 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
6296 adev->pm.current_sclk = adev->clock.default_sclk; in ci_dpm_sw_init()
7704 adev->pm.current_sclk = adev->clock.default_sclk; in si_dpm_sw_init()
