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/Linux-v4.19/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk.dtsi76 clocks = <&clk100 &clk100>;
80 clocks = <&clk100 &clk100>;
84 clocks = <&clk600>, <&clk100>;
88 clocks = <&clk600>, <&clk100>;
92 clocks = <&clk600>, <&clk100>;
96 clocks = <&clk600>, <&clk100>;
100 clocks = <&clk600>, <&clk100>;
104 clocks = <&clk600>, <&clk100>;
108 clocks = <&clk600>, <&clk100>;
112 clocks = <&clk600>, <&clk100>;
[all …]
/Linux-v4.19/arch/arm/boot/dts/
Ds3c2416.dtsi30 clocks: clock-controller@4c000000 { label
41 clocks = <&clocks PCLK_PWM>;
49 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
50 <&clocks SCLK_UART>;
57 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
58 <&clocks SCLK_UART>;
65 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
66 <&clocks SCLK_UART>;
75 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
76 <&clocks SCLK_UART>;
[all …]
Ds5pv210.dtsi59 external-clocks {
88 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
100 clocks: clock-controller@e0100000 { label
104 clocks = <&xxti>, <&xusbxti>;
140 clocks = <&clocks CLK_PDMA0>;
152 clocks = <&clocks CLK_PDMA1>;
167 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
183 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
197 clocks = <&clocks CLK_KEYIF>;
207 clocks = <&clocks CLK_I2C0>;
[all …]
Domap24xx-clocks.dtsi14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
80 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
88 clocks = <&aplls_clkin_ck>;
96 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
105 clocks = <&osc_ck>;
127 clocks = <&sys_ck>, <&sys_ck>;
134 clocks = <&sys_ck>;
[all …]
Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
Domap2430-clocks.dtsi15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
50 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
58 clocks = <&dsp_fck>;
66 clocks = <&dsp_fck>;
76 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
82 clocks = <&core_ck>;
[all …]
Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Dam33xx-clocks.dtsi14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
22 clocks = <&sys_clkin_ck>;
30 clocks = <&sys_clkin_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
Domap54xx-clocks.dtsi20 clocks = <&pad_clks_src_ck>;
40 clocks = <&slimbus_src_clk>;
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
115 clocks = <&dpll_abe_ck>;
121 clocks = <&dpll_abe_x2_ck>;
130 clocks = <&dpll_abe_m2x2_ck>;
138 clocks = <&dpll_abe_m2x2_ck>;
147 clocks = <&aess_fclk>;
156 clocks = <&dpll_abe_m2x2_ck>;
164 clocks = <&dpll_abe_x2_ck>;
[all …]
Ddra7xx-clocks.dtsi14 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
20 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
26 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
32 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
110 clocks = <&sys_clkin1>;
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
209 clocks = <&dpll_abe_ck>;
215 clocks = <&dpll_abe_x2_ck>;
226 clocks = <&dpll_abe_m2x2_ck>;
235 clocks = <&dpll_abe_ck>;
[all …]
Domap2420-clocks.dtsi15 clocks = <&core_ck>;
23 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
31 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
37 clocks = <&sys_clkout2_src>;
47 clocks = <&dsp_fck>;
55 clocks = <&dsp_fck>;
65 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
71 clocks = <&core_ck>;
79 clocks = <&core_ck>;
88 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
[all …]
Domap34xx-omap36xx-clocks.dtsi14 clocks = <&l4_ick>;
22 clocks = <&security_l4_ick2>;
30 clocks = <&security_l4_ick2>;
38 clocks = <&security_l4_ick2>;
46 clocks = <&security_l4_ick2>;
54 clocks = <&dpll4_m5x2_ck>;
63 clocks = <&l4_ick>;
71 clocks = <&core_96m_fck>;
79 clocks = <&l3_ick>;
87 clocks = <&security_l3_ick>;
[all …]
Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
215 clocks = <&mxtal>;
223 clocks = <&mxtal>;
230 clocks = <&pll1>;
238 clocks = <&hclk>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&sys_ck>, <&sys_ck>;
40 clocks = <&dpll5_ck>;
49 clocks = <&core_ck>;
57 clocks = <&core_ck>;
65 clocks = <&core_ck>;
73 clocks = <&core_ck>;
81 clocks = <&dpll4_m2x2_ck>;
89 clocks = <&core_ck>;
[all …]
Domap44xx-clocks.dtsi26 clocks = <&pad_clks_src_ck>;
52 clocks = <&slimbus_src_clk>;
138 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
145 clocks = <&dpll_abe_ck>;
152 clocks = <&dpll_abe_x2_ck>;
163 clocks = <&dpll_abe_m2x2_ck>;
171 clocks = <&dpll_abe_m2x2_ck>;
181 clocks = <&dpll_abe_x2_ck>;
192 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
200 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
[all …]
Domap3430es1-clocks.dtsi14 clocks = <&l3_ick>;
22 clocks = <&l3_ick>;
31 clocks = <&gfx_l3_ck>;
39 clocks = <&gfx_l3_fck>;
47 clocks = <&gfx_l3_fck>;
55 clocks = <&sys_ck>;
63 clocks = <&core_48m_fck>;
71 clocks = <&corex2_fck>;
79 clocks = <&corex2_fck>;
88 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
[all …]
Dsocfpga.dtsi99 clocks = <&l4_main_clk>;
116 clocks = <&can0_clk>;
124 clocks = <&can1_clk>;
132 clocks {
161 clocks = <&osc1>;
167 clocks = <&main_pll>;
175 clocks = <&main_pll>;
183 clocks = <&main_pll>, <&osc1>;
191 clocks = <&main_pll>;
198 clocks = <&main_pll>;
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi14 clocks = <&corex2_fck>;
22 clocks = <&corex2_fck>;
31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
37 clocks = <&ssi_ssr_fck>;
45 clocks = <&core_l3_ick>;
53 clocks = <&l4_ick>;
61 clocks = <&ssi_l4_ick>;
69 clocks = <&omap_96m_fck>;
77 clocks = <&sys_ck>;
85 clocks = <&omap_96m_fck>;
[all …]
Dwm8750.dtsi71 clocks {
90 clocks = <&ref25>;
97 clocks = <&ref25>;
104 clocks = <&ref25>;
111 clocks = <&ref25>;
118 clocks = <&ref25>;
125 clocks = <&plla>;
132 clocks = <&pllb>;
139 clocks = <&pllb>;
146 clocks = <&plld>;
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
[all …]
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
5 gates. This document describes the bindings for those clocks.
10 USB PHY clocks
13 - compatible: shall be "ti,da830-usb-phy-clocks".
15 - clocks: phandles to the parent clocks corresponding to clock-names
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
26 - clocks: phandle to the parent clock
34 - clocks: phandle to the parent clock
42 - clocks: phandles to the parent clocks corresponding to clock-names
50 - clocks: phandles to the parent clocks corresponding to clock-names
[all …]
/Linux-v4.19/drivers/clk/mediatek/
DKconfig19 This driver supports MediaTek MT2701 basic clocks.
25 This driver supports MediaTek MT2701 mmsys clocks.
31 This driver supports MediaTek MT2701 imgsys clocks.
37 This driver supports MediaTek MT2701 vdecsys clocks.
43 This driver supports MediaTek MT2701 hifsys clocks.
49 This driver supports MediaTek MT2701 ethsys clocks.
55 This driver supports MediaTek MT2701 bdpsys clocks.
61 This driver supports Mediatek MT2701 audsys clocks.
67 This driver supports MediaTek MT2701 g3dsys clocks.
75 This driver supports MediaTek MT2712 basic clocks.
[all …]

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