Searched refs:clock_select (Results 1 – 9 of 9) sorted by relevance
95 u8 clock_select; member435 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); in rcar_can_set_bittiming()745 u32 clock_select = CLKR_CLKP1; in rcar_can_probe() local751 "renesas,can-clock-select", &clock_select); in rcar_can_probe()758 clock_select = pdata->clock_select; in rcar_can_probe()792 if (clock_select >= ARRAY_SIZE(clock_names)) { in rcar_can_probe()797 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); in rcar_can_probe()809 priv->clock_select = clock_select; in rcar_can_probe()
160 u16 clock_select; member163 #define mpc52xx_psc_clock_select sr_csr.clock_select311 u8 clock_select; /* PSC + 0x0c */ member
15 enum CLKR clock_select; /* Clock source select */ member
220 val |= params.clock_select << CLKSEL_SHIFT; in ipipeif_hw_setup()316 if (params.clock_select == IPIPEIF_SDRAM_CLK) { in ipipeif_hw_setup()388 ipipeif->config.clock_select = config->clock_select; in ipipeif_set_config()432 config->clock_select = ipipeif->config.clock_select; in ipipeif_get_config()735 .clock_select = IPIPEIF_SDRAM_CLK, in ipipeif_set_default_config()
73 enum ipipeif_clock clock_select; member
82 u32 clock_select; in dice_proc_read() member138 buf.global.clock_select & CLOCK_SOURCE_MASK), in dice_proc_read()140 (buf.global.clock_select & CLOCK_RATE_MASK) in dice_proc_read()
412 VC4_SET_FIELD(vc4_encoder->clock_select, in vc4_crtc_config_pv()1085 vc4_encoder->clock_select = i; in vc4_set_crtc_possible_masks()
393 u32 clock_select; member
54 PPCLK_e clock_select,1609 PPCLK_e clock_select, in vega12_get_clock_ranges() argument1615 *clock = data->clk_range[clock_select].ACMax; in vega12_get_clock_ranges()1617 *clock = data->clk_range[clock_select].ACMin; in vega12_get_clock_ranges()
