Searched refs:clk_ctl (Results 1 – 4 of 4) sorted by relevance
722 int clk_ctl = 0; in sgtl5000_set_clock() local747 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()750 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()753 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; in sgtl5000_set_clock()762 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()765 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()768 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()771 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; in sgtl5000_set_clock()786 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << in sgtl5000_set_clock()790 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << in sgtl5000_set_clock()[all …]
482 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate); in cs35l35_hw_params() local484 if (clk_ctl < 0) { in cs35l35_hw_params()491 CS35L35_CLK_CTL2_MASK, clk_ctl); in cs35l35_hw_params()503 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK; in cs35l35_hw_params()
237 int clk_ctl; member867 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()1013 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()1392 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()1868 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()1872 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1233 static DEVICE_ATTR_RW(clk_ctl);
