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Searched refs:clk_base (Results 1 – 22 of 22) sorted by relevance

/Linux-v4.19/drivers/clk/tegra/
Dclk-tegra210.c298 static void __iomem *clk_base; variable
501 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
514 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
516 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
524 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
538 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
546 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
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Dclk-tegra-super-gen4.c106 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
120 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
130 clk_base + SCLK_DIVIDER, 0, 8, in tegra_sclk_init()
143 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
153 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
157 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
168 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
171 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
176 static void __init tegra_super_clk_init(void __iomem *clk_base, in tegra_super_clk_init() argument
193 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
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Dclk-tegra20.c141 static void __iomem *clk_base; variable
586 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
620 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
642 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
648 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
656 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
662 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
665 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
670 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
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Dclk-tegra30.c159 static void __iomem *clk_base; variable
832 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
838 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
841 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
846 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
852 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
855 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
860 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
870 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
875 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
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Dclk.h325 void __iomem *clk_base; member
351 void __iomem *clk_base, void __iomem *pmc,
356 void __iomem *clk_base, void __iomem *pmc,
361 void __iomem *clk_base, void __iomem *pmc,
367 void __iomem *clk_base, void __iomem *pmc,
373 void __iomem *clk_base, void __iomem *pmc,
379 void __iomem *clk_base, void __iomem *pmc,
385 const char *parent_name, void __iomem *clk_base,
392 void __iomem *clk_base, unsigned long flags,
398 void __iomem *clk_base, unsigned long flags,
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Dclk-tegra114.c141 static void __iomem *clk_base; variable
907 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
927 static void __init tegra114_pll_init(void __iomem *clk_base, in tegra114_pll_init() argument
933 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
939 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
942 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
947 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
952 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
957 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
963 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
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Dclk-periph-gate.c31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
87 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
88 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
90 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
131 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
156 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
Dclk-tegra124.c113 static void __iomem *clk_base; variable
1004 static __init void tegra124_periph_clk_init(void __iomem *clk_base, in tegra124_periph_clk_init() argument
1014 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init()
1019 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); in tegra124_periph_clk_init()
1023 clk_base, 0, 48, in tegra124_periph_clk_init()
1028 clk_base, 0, 82, in tegra124_periph_clk_init()
1032 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1037 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1043 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1048 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); in tegra124_periph_clk_init()
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Dclk-tegra-audio.c141 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, in tegra_audio_sync_clk_init() argument
161 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
170 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
176 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
197 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
207 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
210 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
229 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, in tegra_audio_clk_init()
235 writel_relaxed(1, clk_base + dmic_clks[i].offset); in tegra_audio_clk_init()
237 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, in tegra_audio_clk_init()
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Dclk-periph.c143 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
171 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
172 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
173 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
190 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
194 periph, clk_base, offset, flags); in tegra_clk_register_periph()
199 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
204 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
207 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, in tegra_clk_register_periph_data() argument
212 clk_base, init->offset, init->flags); in tegra_clk_register_periph_data()
Dclk-pll.c241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
313 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
981 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
984 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1118 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1128 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1130 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1140 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1224 void __iomem *clk_base, in _setup_dynamic_ramp() argument
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Dclk-tegra-periph.c882 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
904 clk = tegra_clk_register_periph_data(clk_base, data); in periph_clk_init()
909 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
927 clk_base, data->flags, in gate_clk_init()
934 static void __init div_clk_init(void __iomem *clk_base, in div_clk_init() argument
951 data->p.parent_name, clk_base + data->offset, in div_clk_init()
961 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
972 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
988 clk_base + data->offset, 0, data->div_flags, in init_pllp()
991 data->div_name, clk_base + data->offset, in init_pllp()
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Dclk-sdmmc-mux.c208 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, in tegra_clk_register_sdmmc_mux_div() argument
232 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
234 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
Dclk-tegra-fixed.c32 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
42 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
Dclk.c147 static void __iomem *clk_base; variable
163 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
177 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
214 clk_base = regs; in tegra_clk_init()
/Linux-v4.19/arch/arm/mach-prima2/
Dplatsmp.c23 static void __iomem *clk_base; variable
57 clk_base = of_iomap(np, 0); in sirfsoc_boot_secondary()
58 if (!clk_base) in sirfsoc_boot_secondary()
69 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); in sirfsoc_boot_secondary()
73 clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); in sirfsoc_boot_secondary()
/Linux-v4.19/drivers/clk/
Dclk-npcm7xx.c544 void __iomem *clk_base; in npcm7xx_clk_init() local
557 clk_base = ioremap(res.start, resource_size(&res)); in npcm7xx_clk_init()
558 if (!clk_base) in npcm7xx_clk_init()
575 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
608 mux_data->flags, clk_base + NPCM7XX_CLKSEL, in npcm7xx_clk_init()
628 clk_base + div_data->reg, in npcm7xx_clk_init()
652 iounmap(clk_base); in npcm7xx_clk_init()
/Linux-v4.19/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable() local
48 tmp = __raw_readl(clk_base + S5P_OTHERS); in s5pv210_retention_disable()
51 __raw_writel(tmp, clk_base + S5P_OTHERS); in s5pv210_retention_disable()
60 void __iomem *clk_base; in s5pv210_retention_init() local
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
74 if (!clk_base) { in s5pv210_retention_init()
79 ctrl->priv = (void __force *)clk_base; in s5pv210_retention_init()
/Linux-v4.19/drivers/mmc/host/
Dsdhci-of-at91.c158 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local
170 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; in sdhci_at91_set_clks_presets()
172 gck_rate = clk_base * 1000000 * (clk_mul + 1); in sdhci_at91_set_clks_presets()
187 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; in sdhci_at91_set_clks_presets()
/Linux-v4.19/drivers/cpufreq/
Ds5pv210-cpufreq.c27 static void __iomem *clk_base; variable
30 #define S5P_CLKREG(x) (clk_base + (x))
604 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
606 if (!clk_base) { in s5pv210_cpufreq_probe()
/Linux-v4.19/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c637 static struct clk *clk_base[BASE_CLK_MAX]; variable
639 .clks = clk_base,
648 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
650 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()
/Linux-v4.19/drivers/clk/meson/
Dmeson8b.c25 static void __iomem *clk_base; variable
1103 if (!clk_base) in meson8b_clkc_probe()
1106 map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); in meson8b_clkc_probe()
1155 clk_base = of_iomap(np, 1); in meson8b_clkc_reset_init()
1156 if (!clk_base) { in meson8b_clkc_reset_init()
1166 rstc->base = clk_base; in meson8b_clkc_reset_init()