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Searched refs:cgu (Results 1 – 25 of 27) sorted by relevance

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/Linux-v4.19/drivers/clk/ingenic/
Dcgu.c43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
46 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
61 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
64 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
71 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
82 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
90 clk_info = &cgu->clock_info[ingenic_clk->idx]; in ingenic_pll_recalc_rate()
94 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_recalc_rate()
95 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
96 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_recalc_rate()
[all …]
Djz4740-cgu.c54 static struct ingenic_cgu *cgu; variable
220 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
222 if (!cgu) { in jz4740_cgu_init()
227 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
235 uint32_t lcr = readl(cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
247 writel(lcr, cgu->base + CGU_REG_LCR); in jz4740_clock_set_wait_mode()
252 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
255 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_disable_auto_suspend()
261 uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
264 writel(clkgr, cgu->base + CGU_REG_CLKGR); in jz4740_clock_udc_enable_auto_suspend()
[all …]
Djz4770-cgu.c49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
414 val = readl(cgu->base + CGU_REG_LCR); in jz4770_cgu_pm_suspend()
415 writel(val | LCR_LPM, cgu->base + CGU_REG_LCR); in jz4770_cgu_pm_suspend()
423 val = readl(cgu->base + CGU_REG_LCR); in jz4770_cgu_pm_resume()
[all …]
DMakefile1 obj-y += cgu.o
2 obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o
3 obj-$(CONFIG_MACH_JZ4770) += jz4770-cgu.o
4 obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o
Djz4780-cgu.c98 static struct ingenic_cgu *cgu; variable
114 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
116 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
120 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_parent()
122 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_parent()
132 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
195 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
197 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
200 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
202 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
[all …]
Dcgu.h203 struct ingenic_cgu *cgu; member
231 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
Dingenic,cgu.txt9 - compatible : Should be "ingenic,<soctype>-cgu".
10 For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
18 may be found in <dt-bindings/clock/<soctype>-cgu.h>.
23 cgu: jz4740-cgu {
24 compatible = "ingenic,jz4740-cgu";
30 clocks = <&cgu JZ4740_CLK_UART0>;
49 &cgu {
Dlpc1850-cgu.txt23 Should be "nxp,lpc1850-cgu"
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
126 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
/Linux-v4.19/arch/mips/boot/dts/ingenic/
Djz4780.dtsi2 #include <dt-bindings/clock/jz4780-cgu.h>
39 cgu: jz4780-cgu@10000000 { label
40 compatible = "ingenic,jz4780-cgu";
56 clocks = <&cgu JZ4780_CLK_RTCLK>;
184 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
197 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
210 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
223 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
236 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
246 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
Djz4740.dtsi2 #include <dt-bindings/clock/jz4740-cgu.h>
38 cgu: jz4740-cgu@10000000 { label
39 compatible = "ingenic,jz4740-cgu";
52 clocks = <&cgu JZ4740_CLK_RTC>;
63 clocks = <&cgu JZ4740_CLK_RTC>;
142 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
153 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
161 clocks = <&cgu JZ4740_CLK_UHC>;
162 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
Djz4770.dtsi3 #include <dt-bindings/clock/jz4770-cgu.h>
39 cgu: jz4770-cgu@10000000 { label
40 compatible = "ingenic,jz4770-cgu";
151 clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
164 clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
177 clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
190 clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
203 clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
204 assigned-clocks = <&cgu JZ4770_CLK_UHC>;
Dgcw0.dts29 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
43 &cgu {
50 <&cgu JZ4770_CLK_PLL1>,
51 <&cgu JZ4770_CLK_UHC>;
54 <&cgu JZ4770_CLK_PLL1>;
/Linux-v4.19/arch/arm/boot/dts/
Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dingenic,jz4740-i2s.txt17 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2SPLL>;
/Linux-v4.19/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt57 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu
69 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy
78 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
89 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
101 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
116 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
128 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
/Linux-v4.19/arch/mips/boot/dts/lantiq/
Ddanube.dtsi53 cgu0: cgu@103000 {
54 compatible = "lantiq,cgu-xway";
/Linux-v4.19/drivers/clk/nxp/
DMakefile1 obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
/Linux-v4.19/Documentation/devicetree/bindings/watchdog/
Dingenic,jz4740-wdt.txt15 clocks = <&cgu JZ4740_CLK_RTC>;
Dlpc18xx-wdt.txt16 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
/Linux-v4.19/Documentation/devicetree/bindings/serial/
Dingenic,uart.txt25 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
/Linux-v4.19/Documentation/devicetree/bindings/i2c/
Di2c-jz4780.txt24 clocks = <&cgu JZ4780_CLK_SMB4>;
/Linux-v4.19/Documentation/devicetree/bindings/mmc/
Djz4740.txt33 clocks = <&cgu JZ4780_CLK_MSC0>;
/Linux-v4.19/Documentation/devicetree/bindings/dma/
Djz4780-dma.txt29 clocks = <&cgu JZ4780_CLK_PDMA>;
/Linux-v4.19/Documentation/devicetree/bindings/reset/
Dnxp,lpc1850-rgu.txt68 clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;

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