43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_get()  argument
46 	return !!(readl(cgu->base + info->reg) & BIT(info->bit))  in ingenic_cgu_gate_get()
61 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_set()  argument
64 	u32 clkgr = readl(cgu->base + info->reg);  in ingenic_cgu_gate_set()
71 	writel(clkgr, cgu->base + info->reg);  in ingenic_cgu_gate_set()
82 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_recalc_rate()  local
90 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_pll_recalc_rate()
94 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_recalc_rate()
95 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_recalc_rate()
96 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_recalc_rate()
157 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in to_clk_info()  local
160 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in to_clk_info()
181 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_set_rate()  local
194 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_set_rate()
195 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
206 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
207 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_set_rate()
215 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_enable()  local
223 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_enable()
224 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_enable()
229 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_enable()
233 		ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_enable()
239 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_enable()
250 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_disable()  local
256 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_disable()
257 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_disable()
261 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_disable()
262 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_disable()
268 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_is_enabled()  local
274 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_is_enabled()
275 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_is_enabled()
276 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_is_enabled()
298 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_get_parent()  local
303 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_get_parent()
306 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_get_parent()
326 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_parent()  local
332 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_set_parent()
357 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_parent()
360 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
363 		writel(reg, cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
365 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_parent()
376 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_recalc_rate()  local
381 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_recalc_rate()
384 		div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
427 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_round_rate()  local
431 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_round_rate()
446 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_rate()  local
454 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_set_rate()
463 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_rate()
464 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
480 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
485 				reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
494 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_rate()
504 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_enable()  local
508 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_enable()
512 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_enable()
513 		ingenic_cgu_gate_set(cgu, &clk_info->gate, false);  in ingenic_clk_enable()
514 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_enable()
526 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_disable()  local
530 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_disable()
534 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_disable()
535 		ingenic_cgu_gate_set(cgu, &clk_info->gate, true);  in ingenic_clk_disable()
536 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_disable()
543 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_is_enabled()  local
548 	clk_info = &cgu->clock_info[ingenic_clk->idx];  in ingenic_clk_is_enabled()
551 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_is_enabled()
552 		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);  in ingenic_clk_is_enabled()
553 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_is_enabled()
576 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)  in ingenic_register_clock()  argument
578 	const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];  in ingenic_register_clock()
589 		clk = of_clk_get_by_name(cgu->np, clk_info->name);  in ingenic_register_clock()
601 		cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
618 	ingenic_clk->cgu = cgu;  in ingenic_register_clock()
639 			parent = cgu->clocks.clks[clk_info->parents[i]];  in ingenic_register_clock()
650 		parent = cgu->clocks.clks[clk_info->parents[0]];  in ingenic_register_clock()
713 	cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
724 	struct ingenic_cgu *cgu;  in ingenic_cgu_new()  local
726 	cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);  in ingenic_cgu_new()
727 	if (!cgu)  in ingenic_cgu_new()
730 	cgu->base = of_iomap(np, 0);  in ingenic_cgu_new()
731 	if (!cgu->base) {  in ingenic_cgu_new()
736 	cgu->np = np;  in ingenic_cgu_new()
737 	cgu->clock_info = clock_info;  in ingenic_cgu_new()
738 	cgu->clocks.clk_num = num_clocks;  in ingenic_cgu_new()
740 	spin_lock_init(&cgu->lock);  in ingenic_cgu_new()
742 	return cgu;  in ingenic_cgu_new()
745 	kfree(cgu);  in ingenic_cgu_new()
750 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)  in ingenic_cgu_register_clocks()  argument
755 	cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),  in ingenic_cgu_register_clocks()
757 	if (!cgu->clocks.clks) {  in ingenic_cgu_register_clocks()
762 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
763 		err = ingenic_register_clock(cgu, i);  in ingenic_cgu_register_clocks()
768 	err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,  in ingenic_cgu_register_clocks()
769 				  &cgu->clocks);  in ingenic_cgu_register_clocks()
776 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
777 		if (!cgu->clocks.clks[i])  in ingenic_cgu_register_clocks()
779 		if (cgu->clock_info[i].type & CGU_CLK_EXT)  in ingenic_cgu_register_clocks()
780 			clk_put(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
782 			clk_unregister(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
784 	kfree(cgu->clocks.clks);  in ingenic_cgu_register_clocks()