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Searched refs:cfgcr1 (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.c897 i915_reg_t ctl, cfgcr1, cfgcr2; member
910 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
916 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
922 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
952 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
954 POSTING_READ(regs[id].cfgcr1); in skl_ddi_pll_enable()
1015 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1306 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1320 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_hdmi_pll_dividers()
1334 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
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Dintel_dpll_mgr.h159 uint32_t cfgcr1, cfgcr2; member
Dintel_ddi.c1369 uint32_t cfgcr0, cfgcr1; in cnl_calc_wrpll_link() local
1374 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); in cnl_calc_wrpll_link()
1377 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); in cnl_calc_wrpll_link()
1380 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in cnl_calc_wrpll_link()
1381 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in cnl_calc_wrpll_link()
1383 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in cnl_calc_wrpll_link()
1384 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in cnl_calc_wrpll_link()
Di915_debugfs.c3309 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
Dintel_display.c11554 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()